XC4013XL-1BG256I Xilinx Inc, XC4013XL-1BG256I Datasheet - Page 2

• Manufacturer Part Number: XC4013XL-1BG256I
• Description: IC FPGA I-TEMP 3.3V 1SPD 256PBGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4013XL-1BG256I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 192
• Number Of Gates: 13000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E and XC4000X Series Field Programmable Gate Arrays
D.C. Characteristics Over Recommended Operating Conditions
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The
slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2ms. The current capacity
varies linealy with ramp-up time, e.g. , an XC4036XL with a ramp-up time of 25 ms would require a capacity predicted by the
point on the straight line drawn from 1A at 120 s to 500 mA at 50 ms at the 25 ms time mark. This point is approximately
750 mA
6-74
Note 1:
Note 2:
Symbol
XC4005 - 36XL
XC4044- 62XL
XC4085XL
Notes: 1.
I
I
I
V
V
V
I
CCO
C
RPU
RPD
RLL
I
OH
DR
OL
L
IN
Product
.
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
This specification applies to Commercial and Industrial grade products only.
Ramp-up Time is measured from 0 V
With up to 64 pins simultaneously sinking 12 mA.
With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
The XC4085XL fast ramp-up time is 5 ms.
result in a larger initialization current.
internal power on reset threshold voltage. After initialization and before configuration, I
High-level output voltage @ I
High-level output voltage @ I
Low-level output voltage @ I
Low-level output voltage @ I
Data Retention Supply Voltage (below which configuration data may be lost)
Quiescent FPGA supply current (Note 2)
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
Pad pull-down (when selected) @ V
Horizontal Longline pull-up (when selected) @ logic Low
1
Minimum required current supply
Minimum required current supply
Minimum required current supply
OL
OL
OH
OH
DC
= 12.0 mA, V
= 1500 A, (LVCMOS)
Description
to 3.6 V
= -4.0 mA, V
= -500 A, (LVCMOS)
Description
in
= 0 V (sample tested)
in
= 3.6 V (sample tested)
DC
. Peak current required lasts less than 3 ms, and occurs near the
CC
CC
min (LVTTL) (Note 1)
min (LVTTL)
BGA, SBGA, PQ, HQ, MQ
packages
PGA packages
DS005 (v. 1.8 October 18, 1999 - Product Specification
Fast (120 s)
CC
2 A
1 A
2 A
max is less than 10 mA.
90% V
1
0.02
0.02
Min
-10
2.4
2.5
0.3
Ramp-up Time
CC
10% V
Max
0.25
0.15
+10
Slow (50 ms)
0.4
2.0
10
16
5
500 mA
500 mA
500 mA
CC
Units
mA
mA
mA
mA
pF
pF
V
V
V
V
V
A
R