XC4020E-3HQ240I Xilinx Inc, XC4020E-3HQ240I Datasheet - Page 25
![no-image](/images/no-image-200.jpg)
XC4020E-3HQ240I
Manufacturer Part Number
XC4020E-3HQ240I
Description
IC FPGA I-TEMP 5V 3SPD 240-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4020E-3HQ240I
Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
193
Number Of Gates
20000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4020E-3HQ240I
Manufacturer:
XILINX
Quantity:
3
Table 14: Routing per CLB in XC4000 Series Devices
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
May 14, 1999 (Version 1.6)
Singles
Doubles
Quads
Longlines
Direct
Connects
Globals
Carry Logic
Total
Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
Figure
26).
Vertical Horizontal Vertical Horizontal
R
24
8
4
0
6
0
4
2
Quad
XC4000E
Product Obsolete or Under Obsolescence
Long
18
8
4
0
6
0
0
0
Global
Clock
XC4000E and XC4000X Series Field Programmable Gate Arrays
12
10
45
8
4
2
8
1
Long
XC4000X
Double Single Global
12
32
8
4
6
2
0
0
Single-Length Lines
Single-length lines provide the greatest interconnect flexi-
bility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switch-
ing matrices that are located in every row and a column of
CLBs.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in
connectivity is shown in
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for rout-
ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
Figure 26: Programmable Switch Matrix (PSM)
Clock
Singles
Double
Double
Chain
Carry
CLB
Connect
Direct
Figure
27.
x5994
Quad
Single
Double
Long
Direct
Connect
Long
Figure
Six Pass Transistors
Interconnect Point
Per Switch Matrix
28. Routing
X6600
6-29
6