XC4036XL-09BG352C Xilinx Inc, XC4036XL-09BG352C Datasheet - Page 7

• Manufacturer Part Number: XC4036XL-09BG352C
• Description: IC FPGA C-TEMP 3.3V 352-MBGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4036XL-09BG352C

• Number Of Logic Elements/cells: 3078
• Number Of Labs/clbs: 1296
• Total Ram Bits: 41472
• Number Of I /o: 288
• Number Of Gates: 36000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 352-LBGA, Metal
• Case: BGA
• Dc: 00+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I/O Signalling Standards
XLA and XV devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in
illustrated in
VCC Clamping
XLA/XV devices are fully 5V TTL I/O compatible if VCC
clamping is not enabled. The I/O pins can withstand input
voltages up to 7V. With VCC clamping enabled, the XLA/XV
devices will begin to clamp input voltages to one diode volt-
age drop above VCC. In both cases negative voltage is
clamped to one diode voltage drop below ground.
Table 6: I/O Standards supported by XC4000XLA and XV FPGAs
Express Configuration Mode
Express configuration mode is similar to Slave Serial con-
figuration mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An external
source is used to drive CCLK, while byte-wide data is
loaded directly into the configuration data shift registers
(Figure
80 MHz serial rate, because eight bits of configuration data
are loaded per CCLK cycle. Express mode does not sup-
DS015 (v1.3) October 18, 1999 - Product Specification
Figure 4: The Signalling Environment for XLA/XV FPGAS. For XLA devices the VCCIO and VCCINT supplies are
replaced by a single 3.3 Volt VCC supply, however, all indicated I/O signalling is still supported.
LVCMOS 3V
Signaling
Standard
LVTTL
PCI5V
PCI3V
TTL
5). A CCLK frequency of 10 MHz is equivalent to a
Figure
R
Not allowed
Not allowed
Table 6
Clamping
5.0 V Power
3.3 V Power
2.5 V Power
Ground
Required
4.
VCC
OK
OK
and the signaling environment is
5 Volt Device
V
CC
Output Drive
(5 V)
12/24 mA
12/24 mA
12/24 mA
24 mA
12 mA
LVTTL
TTL
V
IH_MAX
5.5
3.6
5.5
3.6
3.6
V
CCIO
XC4000XV
XC4000XLA/XV Field Programmable Gate Arrays
V
CCINT
VCC/VCCIO
VCC/VCCIO
XLA/XV devices maintain LVTTL I/O compatibility when
VCC clamping is enabled, however full 5.0V TTL I/O com-
patibility is sacrificed.
Overshoot and Undershoot
Ringing wave forms are allowed on XLA/XV inputs as long
as undershoot is limited to -2.0V and overshoot is limited to
+7.0V and current is limited to 100 mA for less than 10 ns.
If VCC clamping is enabled then overshoot will begin to be
clamped at VCC/VCCIO plus one diode voltage drop and
undershoot will be clamped to ground minus one diode volt-
age drop. In either case the current must be limited to 100
mA per pin for less than 10 ns.
port CRC error checking, but does support constant-field
error checking. A length count is not used in Express mode.
Express mode must be specified as an option to the BitGen
program, which generates the bitstream. The Express
mode bitstream is not compatible with the other configura-
tion modes. Express mode is selected by a <010> on the
mode pins (M2, M1, M0).
The first byte of parallel configuration data must be avail-
able at the D inputs of the FPGA a short setup time before
the second rising CCLK edge. Subsequent data bytes are
V
50% of
50% of
IH MIN
2.0
2.0
2.0
LVTTL
VCC/VCCIO
VCC/VCCIO
3.3 Volt Device
V
30% of
30% of
V
IL MAX
0.8
0.8
0.8
CC
(3.3 V)
VCC/VCCIO
VCC/VCCIO
X7147
V
90% of
90% of
OH MIN
2.4
2.4
2.4
VCC/VCCIO
VCC/VCCIO
V
10% of
10% of
OL MAX
0.4
0.4
0.4
6-163
6