AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 178
![IC FPSLIC 5K GATE 25MHZ 84PLCC](/photos/6/70/67047/453-84-plcc_sml.jpg)
AT94K05AL-25AJI
Manufacturer Part Number
AT94K05AL-25AJI
Description
IC FPSLIC 5K GATE 25MHZ 84PLCC
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K05AL-25AJI
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
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6.4
All input IO characteristics measured from a V
V
178
Cell Function
Repeaters
Repeater
Repeater
Repeater
Repeater
Repeater
Repeater
Cell Function
IO
Input
Input
Input
Input
Output, Slow
Output, Medium
Output, Fast
Output, Slow
Output, Slow
Output, Medium
Output, Medium
Output, Fast
Output, Fast
DD
. All output IO characteristics are measured as the average of t
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Maximum delays are the average of t
All input IO characteristics measured from a V
output IO characteristics are measured as the average of t
AT94KAL Series FPSLIC
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
t
t
t
t
t
t
PD
PD
PD
PD
PD
PD
PD
PZX
PXZ
PZX
PXZ
PZX
PXZ
PD
PD
PD
PD
PD
PD
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
PDLH
CC
CC
= 3.6V, temperature = 0° C
and t
= 3.0V, temperature = 70° C
IH
of 50% of V
IH
PDHL
of 50% of V
.
Path
pad -> x/y
pad -> x/y
pad -> x/y
pad -> x/y
x/y/E/L -> pad
x/y/E/L -> pad
x/y/E/L -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
L -> E
E -> E
L -> L
E -> L
E -> IO
L -> IO
Path
PDLH
DD
DD
at the pad (CMOS threshold) to the internal V
at the pad (CMOS threshold) to the internal V
and t
PDLH
PDHL
and t
to the pad V
PDHL
to the pad V
11.5
17.4
-25
1.9
5.8
9.1
7.6
6.2
9.5
2.1
7.4
2.7
5.9
2.4
-25
2.2
2.2
2.2
2.2
1.4
1.4
IH
of 50% of V
Units
Units
IH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
of 50% of V
DD
.
Notes
No Extra Delay
1 Extra Delay
2 Extra Delays
3 Extra Delays
50 pf Load
50 pf Load
50 pf Load
50 pf Load
50 pf Load
50 pf Load
50 pf Load
50 pf Load
50 pf Load
1 Unit Load
1 Unit Load
1 Unit Load
1 Unit Load
1 Unit Load
1 Unit Load
Notes
IH
of 50% of V
DD
1138I–FPSLI–1/08
.
IH
of 50% of
DD
. All
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