AT94K05AL-25BQC Atmel, AT94K05AL-25BQC Datasheet - Page 174
AT94K05AL-25BQC
Manufacturer Part Number
AT94K05AL-25BQC
Description
IC FPSLIC 5K GATE 25MHZ 144LQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K05AL-25BQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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6.1.1
Table 6-2.
Table 6-3.
174
Symbol
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
ADS
ADH
RDS
RDH
ACC
MEH
MEl
ADS
ADH
WRS
MPW
WDS
WDH
AT94KAL Series FPSLIC
Frame Interface
Parameter
Address Setup
Address Hold
Read Cycle Setup
Read Cycle Hold
Access Time from Posedge ME
Minimum ME High
Minimum ME Low
Parameter
Address Setup
Address Hold
Write Cycle Setup
Minimum Write Duration
Data Setup to Write End
Data Hold to Write End
SRAM Read Cycle Timing Numbers
Commercial 3.3V ± 10%/Industrial 3.3V ± 10%
SRAM Write Cycle Timing Numbers
Commercial 3.3V ± 10%/Industrial 3.3V ± 10%
The FPGA Frame Clock phase is selectable (see
page
relation of ME to data, address and write enable does not change). By default, FrameClock is
inverted (ME = ~FrameClock). Selecting the non-inverted phase assigns ME = FrameClock.
Recall, the Dual-port SRAM operates in single-edge clock controlled mode during read opera-
tions, and double-edge clock controlled mode during writes. Addresses are clocked internally on
the rising edge of the clock signal (ME). Any change of address without a rising edge of ME is
not considered.
30). This document refers to the clock at the FPGA/Dual-port SRAM interface as ME (the
Minimum
Minimum
0.6
0.7
3.4
0.7
0.6
0.6
0.7
1.4
4.6
0.6
0
0
0
Commercial
Commercial
Typical
Typical
0.8
0.9
4.2
0.9
0.8
0.8
0.9
1.8
5.7
0.8
0
0
0
Maximum
Maximum
1.1
1.3
5.9
1.1
1.3
8.0
1.3
1.1
2.5
1.1
0
0
0
“System Control Register – FPGA/AVR” on
Minimum
Minimum
0.5
0.6
2.9
0.6
0.6
0.5
0.6
1.2
3.9
0.5
0
0
0
Industrial
Industrial
Typical
Typical
0.8
0.9
4.2
0.9
0.8
0.8
0.9
1.8
5.7
0.8
0
0
0
Maximum
Maximum
1.2
1.5
6.9
1.5
1.2
1.5
3.0
1.3
9.4
1.3
0
0
0
1138I–FPSLI–1/08
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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