FMS7401LVN Fairchild Semiconductor, FMS7401LVN Datasheet - Page 15

• Manufacturer Part Number: FMS7401LVN
• Description: IC CTRLR POWER DGTL EEPROM 8DIP
• Manufacturer: Fairchild Semiconductor

Specifications of FMS7401LVN

• Applications: Digital Power Controller
• Core Processor: 8-Bit
• Program Memory Type: EEPROM (1 kB)
• Ram Size: 64 x 8
• Number Of I /o: 6
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Output Current: 5 mA
• Input Voltage: 2.7 V to 3.6 V
• Switching Frequency: 2 MHz
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Controller Series: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: FMS7401LVN_NL; FMS7401LVN_NL

1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit.
2. If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must
3.
4.
5.
6.
1. The MIW and Timer 0 Circuits are described later in the datasheet.
2. Refer to the
3. Refer to the
4. The FSEL bit in the PSCALE register must be set.
REV. 1.0.3 1/24/05
PRODUCT SPECIFICATION
be set after the appropriate T
Prior to entering Idle Mode, software must clear both FMODE and FSEL (the timer must be disabled in order to clear
either bit) keeping the PLLEN bit 1.
Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit.
Software may then instruct the device to enter Idle Mode.
If all disabled circuits must be re-enabled after exiting from Idle Mode, repeat all initial steps enabling all circuits in the
appropriate order as well as waiting T
Electrical Characteristics
Clock Circuit’s PLL
section of the datasheet for details.
section of the datasheet for details.
PLL_LOCK
PLL_LOCK
wait time.
.
FMS7401L
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