CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 141

• Manufacturer Part Number: CY8CTMG200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2954

16.4.4
Timing and functionality details are summarized in
for IPOR, PPOR, XRES, and WDR.
Table 16-1. Reset Functionality
a. CPU reset is released after synchronization with the CPU clock.
b. Measured from CPU reset release to execution of the code at Flash address 0x0000.
16.5
The ILO block drives the CLK32K clock used to time most
events during the reset sequence. This clock is powered
down by IPOR but not by any other reset. The sleep timer
provides interval timing.
While POR or XRES assert, the IMO is powered off to
reduce startup power consumption.
During and following IRES (for 64 ms nominally), the IMO is
powered off for low average power during slow supply
ramps.
During and after POR or XRES, the bandgap circuit is pow-
ered up.
The IMO is always on for at least one CLK32K cycle before
CPU reset is deasserted.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Reset Length
Low Power (IMO Off) During Reset?
Low Power Wait Following Reset?
CLK32K Cycles from End of Reset to
CPU Reset Deasserts
Register Reset
(See Next Line for CPU_SCR0,
CPU_SCR1)
Reset Status Bits in CPU_SCR0,
CPU_SCR1
Bandgap Power
Boot Time
b
Power Modes
Reset Details
Item
a
IPOR (Part of POR)
Clear IRAMDIS
While POR=1
Clear WDRS,
Set PORS,
2.2 ms
Yes
512
No
On
All
Table
16-1.
All, except PPOR does not
PPOR (Part of POR)
30-60 µs (1-2 clocks)
While PPOR=1, plus
reset Bandgap Trim
Clear IRAMDIS
Clear WDRS,
Figure 16-4 on page 140
Set PORS,
register
2.2 ms
Yes
No
On
1
Clear IRAMDIS
While XRES=1
Clear WDRS,
Set PORS,
2.2 ms
XRES
shows some of the relevant signals
Yes
On
No
All
8
IRAMDIS unchanged
30 µs (1 clock)
Clear PORS,
Set WDRS,
System Resets
2.2 ms
WDR
No
No
On
All
1
141
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