XE8801AMI027LF Semtech, XE8801AMI027LF Datasheet - Page 77
XE8801AMI027LF
Manufacturer Part Number
XE8801AMI027LF
Description
IC DAS 16BIT FLASH 8K MTP 44LQFP
Manufacturer
Semtech
Datasheet
1.XE8801AMI027LF.pdf
(135 pages)
Specifications of XE8801AMI027LF
Applications
Sensing Machine
Core Processor
RISC
Program Memory Type
FLASH (22 kB)
Controller Series
XE8000
Ram Size
512 x 8
Interface
UART, USRT
Number Of I /o
24
Voltage - Supply
2.4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LQFP
For Use With
XE8000MP - PROG BOARD AND PROSTART2 CARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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The bits UartEnRx1 and UartEnRx2 are used to enable or disable the reception. When one is set to 1, the
reception is enabled.
The word length (7 or 8 data bits) can be chosen with UartWL. A parity bit is added during transmission or checked
during reception if UartPE is set. The parity mode (odd or even) can be chosen with UartPM.
Setting the bits UartXRx and UartXTx inverts the Rx respectively Tx signals.
The bit UartEcho is used to send the received data automatically back. The transmission function becomes then:
Tx = Rx XOR UartXTx.
14.6.2
In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent has to be
written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goes to 1, indicating to the transmitter
that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the
contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is
generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows
that the transmitter is busy transmitting a word.
A timing diagram is shown in Figure 14-1. Data are sent LSB first.
New data should be written to the register RegUartTx only while UartTxFull is 0, otherwise data will be lost.
Figure 14-1. Uart transmission timing diagram.
© Semtech 2005
Asynchronous Transmission
Asynchronous Transmission (back to back)
write to RegUartTx
write to RegUartTx
reguarttx_shift
reguarttx_shift
UartTxBusy
UartTxBusy
RegUartTx
Irq_uart_Tx
RegUartTx
Irq_uart_Tx
UartTxFull
UartTxFull
shift clock
shift clock
Transmission
Tx
Tx
word 1
word 1
word 1
start
word 2
word 1
start
word 2
word 1
b0
b0
14-5
b1
b6/7
stop
b6/7
word 2
start
parity
XE8801A – SX8801R
stop
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