CY7C68013A-100AXI Cypress Semiconductor Corp, CY7C68013A-100AXI Datasheet - Page 42

• Manufacturer Part Number: CY7C68013A-100AXI
• Description: IC MCU USB PERIPH HI SPD 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-100AXI

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2263; CY7C68013A-100AXI

10.6 GPIF Synchronous Signals
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
20. Dashed lines denote signals with programmable polarity.
21. GPIF asynchronous RDY
22. IFCLK must not exceed 48 MHz.
Parameter
Parameter
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
x
signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
X
X
to Clock Setup Time
to Clock Setup Time
GPIFADR[8:0]
DATA(output)
DATA(input)
X
X
Figure 17. GPIF Synchronous Signals Timing Diagram
X
[22]
X
Output Propagation Delay
Output Propagation Delay
IFCLK
RDY
CTL
X
X
Description
Description
t
SRY
t
SGD
t
XCTL
N
t
XGD
t
IFCLK
valid
t
RYH
t
t
DAH
SGA
N+1
20.83
20.83
Min.
Min
8.9
9.2
2.9
3.7
3.2
4.5
0
0
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[20, 21]
[21]
[20]
Max.
Max
11.5
10.7
200
7.5
6.7
11
15
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Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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