ADE7169ASTZF16 Analog Devices Inc, ADE7169ASTZF16 Datasheet - Page 101

• Manufacturer Part Number: ADE7169ASTZF16
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7169ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADE7169EBZ-2 - BOARD EVALUATION FOR ADE7169F16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C)
Bit
7
6
[5:0]
1
Table 90. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5]
0
1
1
Table 91. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit
7
6
[5:2]
1
0
Table 92. LCD Clock SFR (LCDCLK, Address 0x96)
Bit
[7:6]
[5:4]
[3:0]
This feature is not available in the ADE7116.
This feature is not available in the ADE7116.
Mnemonic
Reserved
EXTRES
BIASLV
Mnemonic
Reserved
INV_LVL
Reserved
UPDATEOVER
REFRESH
Mnemonic
BLKMOD
BLKFREQ
FD
V
V
V
A
REF
REF
(V)
×
×
⎛
⎜
⎝
BLVL
1
+
31
BLVL
[ ]
4
Default
0
0
0
Default
0
0
0000
0
0
Default
0
0
0
:
0
31
[ ]
4
0 :
⎞
⎟
⎠
Description
Reserved.
External resistor ladder selection bit.
EXTRES
0
1
Bias level selection bits. See Table 90.
Description
This bit should be kept cleared for proper operation.
Frame inversion mode enable bit. If this bit is set, frames are inverted every other frame. If this bit is
cleared, frames are not inverted.
These bits should be kept cleared to 0 for proper operation.
Update finished flag bit. This bit is updated by the LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
Refresh LCD data memory bit. This bit should be set by the user. When set, the LCD driver does not
use the data in the LCD data registers to update the display. The LCD data registers can be updated
by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display
at the next frame.
Description
Blink mode clock source configuration bits.
BLKMOD
00
01
10
11
Blink rate configuration bits. These bits control the LCD blink rate if the BLKMOD bits = 11.
BLKFREQ
00
01
10
11
LCD frame rate selection bits. See Table 93 and Table 94.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
V
V
V
B
B
B
= V
= V
Result
External resistor ladder is disabled. Charge pump is enabled.
External resistor ladder is enabled. Charge pump is disabled.
Rev. B | Page 101 of 152
A
A
Result
The blink rate is controlled by software; the display is off.
The blink rate is controlled by software; the display is on.
The blink rate is 2 Hz.
The blink rate is set by BLKFREQ.
Result (Blink Rate)
1 Hz
1/2 Hz
1/3 Hz
1/4 Hz
1
1/2 Bias
1
V
V
V
C
C
C
= 2 × V
= 2 × V
A
A
V
V
V
B
B
B
= 2 × V
= 2 × V
A
A
1/3 Bias
V
V
V
C
C
C
= 3 × V
= 3 × V
A
A