CY8C20666-24LTXI Cypress Semiconductor Corp, CY8C20666-24LTXI Datasheet
CY8C20666-24LTXI
Specifications of CY8C20666-24LTXI
CY8C20666-24LTXI
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CY8C20666-24LTXI Summary of contents
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... Partial Flash Updates ❐ Flexible Protection Modes ❐ In-System Serial Programming (ISSP) ❐ Full Speed USB ■ Available on CY8C20646, CY8C20666, CY8C20x96 Only ❐ 12 Mbps USB 2.0 Compliant ❐ Eight Unidirectional Endpoints ❐ One Bidirectional Control Endpoint ❐ Dedicated 512 Byte Buffer ❐ ...
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Logic Block Diagram PSoC CORE SYSTEM BUS 1K/2K Supervisory ROM (SROM) SRAM Interrupt Controller 6/12/24 MHz Internal Main Oscillator CAPSENSE SYSTEM Two Comparators SYSTEM BUS I2C USB Slave References Document Number: 001-12696 Rev. *E Port 4 Port 3 Port 2 ...
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PSoC Functional Overview The PSoC family consists of on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable ...
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Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: ...
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Development Tools ® PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable System-on- Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows XP and Windows Vista. This system provides design database management by project, ...
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Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification ...
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Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 1. Acronyms Acronym Description AC alternating current API application programming interface CPU central processing unit DC direct current FSR full scale range GPIO ...
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Pinouts The CY8C20x36/46/66/96 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. ...
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QFN Table 3. Pin Definitions - CY8C20336, CY8C20346 Type Pin Name No. Digital Analog 1 I/O I P2[5] Crystal output (XOut) 2 I/O I P2[3] Crystal input (XIn) 3 I/O I P2[1] 4 IOHR I P1[7] I2C SCL, SPI ...
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QFN with USB Table 4. Pin Definitions - CY8C20396 PSoC Device Type Pin No. Name Digital Analog 1 I/O I P2[5] 2 I/O I P2[3] 3 I/O I P2[1] 4 IOHR I P1[7] I2C SCL, SPI SS 5 IOHR ...
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QFN Table 5. Pin Definitions - CY8C20436, CY8C20446, [2, 3] CY8C20466 PSoC Device Type Pin Name No. Digital Analog 1 IOH I P0[1] Integrating input 2 I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I ...
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QFN (with USB) Table 6. Pin Definitions - CY8C20496 PSoC Device Type Pin Name No. Digital Analog 1 IOH I P0[1] 2 I/O I P2[5] XTAL Out 3 I/O I P2[3] XTAL In 4 I/O I P2[1] 5 IOHR ...
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SSOP Table 7. Pin Definitions - CY8C20536, CY8C20546, [2] and CY8C20566 PSoC Device Name Description 1 IOH I P0[7] 2 IOH I P0[5] 3 IOH I P0[3] 4 IOH I P0[1] 5 I/O I P2[7] 6 I/O I P2[5] ...
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QFN Table 8. Pin Definitions - CY8C20636 PSoC Device Pin Name Description No connection 2 I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 I/O I P2[1] ...
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... QFN with USB Table 9. Pin Definitions - CY8C20646, CY8C20666 PSoC Device Pin Name Description No connection 2 I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 I/O I P2[1] 6 I/O I P4[3] 7 I/O I P4[1] 8 I/O I P3[7] 9 I/O I P3[5] 10 I/O I P3[3] 11 I/O I P3[1] ...
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QFN OCD The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit [4] debugging. Table 10. Pin Definitions - CY8C20066 PSoC Device Pin Name No. 1 OCDOE ...
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Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36/46/66/96 PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at Figure 10. Voltage versus CPU ...
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Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol Description T Storage Temperature STG Vdd Supply Voltage Relative to Vss V DC Input Voltage ...
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DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage I Supply Current, IMO = 24 MHz DD24 I Supply Current, ...
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Table 15. 3.0V to 5.5V DC GPIO Specifications (continued) Symbol Description V High Output Voltage OH10 Port 1 Pins with LDO Enabled for 1.8V Out V Low Output Voltage OL V Input Low Voltage IL V Input High Voltage IH ...
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Table 16. 2.4V to 3.0V DC GPIO Specifications Symbol Description R Pull up Resistor PU V High Output Voltage OH1 Port Pins V High Output Voltage OH2 Port Pins V High Output Voltage OH3 ...
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Table 17. 1.71V to 2.4V DC GPIO Specifications (continued) Symbol Description V Input Hysteresis Voltage H I Input Leakage (Absolute Value Capacitive Load on Pins PIN Table 18.DC Characteristics – USB Interface Symbol Description Rusbi USB D+ Pull ...
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Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V. ...
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DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. DC POR and LVD Specifications Symbol Description Vdd Value for PPOR Trip V PORLEV[1:0] = 00b, HPOR ...
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AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 25. AC Chip-Level Specifications Symbol Description F CPU Frequency CPU F Internal Low Speed Oscillator Frequency 32K1 F Internal Main ...
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AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 26. AC GPIO Specifications Symbol Description F GPIO Operating Frequency GPIO TRise23 Rise Time, Strong Mode, Cload = ...
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Table 27.AC Characteristics – USB Data Timings Symbol Description Tdrate Full speed data rate Tdjr1 Receiver data jitter tolerance Tdjr2 Receiver data jitter tolerance Tudj1 Driver differential jitter Tudj2 Driver differential jitter Tfdeop Source jitter for differential transition Tfeopt Source ...
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AC Programming Specifications SCLK (P1[1]) T RSCLK SDATA (P1[0]) T SSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 32. AC Programming Specifications Symbol Description T Rise Time of SCLK ...
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AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 33. AC Characteristics of the I2C SDA and SCL Pins Symbol F SCL Clock Frequency SCLI2C T Hold Time (repeated) ...
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Table 34. SPI Master AC Specifications Symbol Description F SCLK clock frequency SCLK DC SCLK duty cycle T MISO to SCLK setup time SETUP T SCLK to MISO hold time HOLD T SCLK to MOSI valid time OUT_VAL T MOSI ...
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Packaging Information This section illustrates the packaging specifications for the CY8C20x36/46/66/96 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a ...
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Document Number: 001-12696 Rev. *E Figure 16. 24-Pin (4x4 x 0.6 mm) QFN Figure 17. 32-Pin (5x5 x 0.6 mm) QFN CY8C20X36/46/66/96 001-13937 *B 001-42168 *C Page [+] Feedback ...
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BSC 0.008 0.0135 Important Notes For information on the preferred dimensions for mounting QFN packages, see the following Application Note at ■ http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Pinned vias for thermal conduction are not required for the ...
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Thermal Impedances Table 36. Thermal Impedances per Package Package 16 QFN [13] 24 QFN [13] 32 QFN 48 SSOP [13] 48 QFN Solder Reflow Peak Temperature This table lists the minimum solder reflow peak temperature to achieve good solderability. Table ...
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Development Tool Selection Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler. PSoC ...
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... CY8C20566-24PVXI 48 SSOP CY8C20636-24LTXI 48 QFN CY8C20646-24LTXI 48 QFN CY8C20666-24LTXI 48 QFN Third-Party Tools Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer Application Note “ ...
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... Pin (7x7 mm) QFN CY8C20646-24LTXI 48 Pin (7x7 mm) QFN CY8C20646-24LTXIT (Tape and Reel) 48 Pin (7x7 mm) QFN CY8C20666-24LTXI 48 Pin (7x7 mm) QFN CY8C20666-24LTXIT (Tape and Reel) [4] 48 Pin (7x7 mm) QFN (OCD) CY8C20066-24LTXI Notes 18. Dual-function Digital I/O Pins also connect to the common analog mux. Document Number: 001-12696 Rev. *E ...
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Document History Page Document Title: CY8C20x36/46/66/96 CapSense Document Number: 001-12696 Revision ECN Origin of Change ** 766857 HMT *A 1242866 HMT *B 2174006 AESA *C 2587518 TOF/JASM/MNU/ HMT *D 2649637 SNV/AESA *E 2700196 SNV/PYRS Document Number: 001-12696 Rev. *E Applications ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...