ATAM862P-TNQY3D Atmel, ATAM862P-TNQY3D Datasheet - Page 44
![IC MCU FLASH 4K TX 315MHZ 24SSOP](/photos/6/76/67636/453-24-ssop_sml.jpg)
ATAM862P-TNQY3D
Manufacturer Part Number
ATAM862P-TNQY3D
Description
IC MCU FLASH 4K TX 315MHZ 24SSOP
Manufacturer
Atmel
Datasheet
1.ATAM862P-TNQY3D.pdf
(110 pages)
Specifications of ATAM862P-TNQY3D
Applications
UHF ASK/FSK
Core Processor
MARC4
Program Memory Type
FLASH (4 kB)
Controller Series
MARC4 4-Bit
Ram Size
256 x 4
Interface
SSI
Number Of I /o
11
Voltage - Supply
1.8 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Processor Series
ATAM862x
Core
MARC4
Data Bus Width
4 bit
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ATAM862-3
This timer starts running automatically after any power-on reset! If the watchdog function is not
activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog
timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system
reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it
overflows. The application software has to accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization
routine. There are two watchdog modes, in one mode the watchdog can be switched on and off
by software, in the other mode the watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be pro-
grammed via the watchdog control register (WDC).
Figure 22-7. Timer 1 Module
Figure 22-8. Timer 1 and Watchdog
CL1
T1C1 register
Write of the
T1C1
WDC
T1RM T1C2 T1C1 T1C0
SUBCL
SYSCL
WDL
WDR WDT1 WDT0
Decoder
Decoder
3
RES
CL
MUX
T1CS
2
Q1 Q2 Q3 Q4
CL1
mode control
Watchdog
RES
Q5
MUX for watchdog timer
Prescaler
MUX for interval timer
14 bit
Q6
T1MUX
Q8
Q8
WDCL
T1BP
Q11
Q11
T1IM
Watchdog
4 bit
Q14
Q14
T1C2
T1MUX
SUBCL
WDCL
T1BP T1IM
Divider / 8
Watchdog
NRST
INT2
T1OUT
Divider
RESET
4554F–4BMCU–07/07
CWD register
T1IM=0
T1IM=1
Read of the
INT2
T1OUT
RESET
(NRST)
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