ADE7566ASTZF8 Analog Devices Inc, ADE7566ASTZF8 Datasheet
ADE7566ASTZF8
Specifications of ADE7566ASTZF8
Available stocks
Related parts for ADE7566ASTZF8
ADE7566ASTZF8 Summary of contents
Page 1
GENERAL FEATURES Wide supply voltage operation: 2 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power-saving modes (PSM) Full operation 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA ...
Page 2
ADE7566/ADE7569/ADE7166/ADE7169 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features........................................................ 1 Microprocessor Features.................................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagrams............................................................. 4 Specifications..................................................................................... 6 Energy Metering ........................................................................... 6 Analog Peripherals ....................................................................... 7 Digital Interface ............................................................................ ...
Page 3
LCD Registers ..............................................................................96 LCD Setup ....................................................................................99 LCD Timing and Waveforms ....................................................99 Blink Mode................................................................................ 100 Display Element Control......................................................... 100 Voltage Generation .................................................................. 101 LCD External Circuitry........................................................... 101 LCD Function in PSM2........................................................... 101 Flash Memory ............................................................................... 103 Overview ................................................................................... 103 Flash Memory ...
Page 4
ADE7566/ADE7569/ADE7166/ADE7169 GENERAL DESCRIPTION The ADE7566/ADE7569/ADE7166/ADE7169 Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to make an electronic energy meter ...
Page 5
REF SPI/I SERIAL INTERFACE + PGA1 ADC I – ENERGY – MEASUREMENT PGA1 ADC DSP PGA2 ADC V – ...
Page 6
ADE7566/ADE7569/ADE7166/ADE7169 SPECIFICATIONS V = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz ENERGY METERING Table 2. Parameter 1 MEASUREMENT ACCURACY Phase Error Between Channels PF = 0.8 Capacitive PF = ...
Page 7
ANALOG PERIPHERALS Table 3. Parameter INTERNAL ADCs (BATTERY, TEMPERATURE, V Power Supply Operating Range 1 No Missing Codes 2 Conversion Delay ADC Gain V Measurement DCIN V Measurement BAT Temperature Measurement ADC Offset V Measurement DCIN V ...
Page 8
ADE7566/ADE7569/ADE7166/ADE7169 Parameter LCD, RESISTOR LADDER ACTIVE Leakage Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage ON-CHIP REFERENCE Reference Error Power Supply Rejection Temperature Coefficient 1 1 These numbers are not production tested but are guaranteed ...
Page 9
Parameter POWER SUPPLY INPUTS BAT INTERNAL POWER SUPPLY SWITCH (V SWOUT Resistance BAT SWOUT Resistance DD SWOUT ←→ Switching Open Time BAT DD BCTRL State Change and ...
Page 10
ADE7566/ADE7569/ADE7166/ADE7169 TIMING SPECIFICATIONS AC inputs during testing were driven at V and 0.45 V for Logic 0. Timing measurements were made at V minimum for Logic 1 and V maximum for Logic 0, as shown in IL Figure 3. For ...
Page 11
Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge ...
Page 12
ADE7566/ADE7569/ADE7166/ADE7169 Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge ...
Page 13
Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data ...
Page 14
ADE7566/ADE7569/ADE7166/ADE7169 Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
Page 15
ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 11. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND, V ...
Page 16
ADE7566/ADE7569/ADE7166/ADE7169 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 COM3/FP27 Common Output 3 or LCD Segment Output ...
Page 17
Pin No. Mnemonic Description 43 P0.2/CF1/RTCCAL General-Purpose Digital I/O Port 0.2, Calibration Frequency Logic Output 1, or RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, I The RTCCAL logic output gives access to the calibrated ...
Page 18
ADE7566/ADE7569/ADE7166/ADE7169 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 MID CLASS C GAIN = 1 INTEGRATOR OFF 1.5 INTERNAL REFERENCE 1.0 0.5 +25° +85° –40° –0.5 –1.0 –1.5 MID CLASS C –2.0 0.1 1 ...
Page 19
GAIN = 1 INTEGRATOR OFF 0.4 INTERNAL REFERENCE 0.3 0 3.3V rms I ; 3.3V rms 0 3.43V rms 0 –0 3.13V rms –0.2 –0.3 –0.4 –0.5 0.1 1 CURRENT CHANNEL (% of ...
Page 20
ADE7566/ADE7569/ADE7166/ADE7169 2.0 MID CLASS C GAIN = 16 INTEGRATOR OFF 1.5 INTERNAL REFERENCE 1.0 0.5 +25° –40° –0.5 +85° –1.0 –1.5 MID CLASS C –2.0 0.1 1 CURRENT CHANNEL (% ...
Page 21
GAIN = 16 MID CLASS C INTEGRATOR ON 1.5 INTERNAL REFERENCE 1.0 –40° +85° 0.5 +25° 0.5 0.5 –40° 0.5 0 +25° +85° –0.5 ...
Page 22
ADE7566/ADE7569/ADE7166/ADE7169 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7566/ADE7569/ADE7166/ADE7169 is defined by the following formula: ⎛ − Energy Register True ⎜ = Percentage Error ⎜ True Energy ⎝ Phase Error Between Channels The digital ...
Page 23
SFR MAPPING Table 14. Mnemonic Address INTPR 0xFF SCRATCH4 0xFE SCRATCH3 0xFD SCRATCH2 0xFC SCRATCH1 0xFB BATVTH 0xFA STRBPER 0xF9 IPSMF 0xF8 TEMPCAL 0xF7 RTCCOMP 0xF6 BATPR 0xF5 PERIPH 0xF4 DIFFPROG 0xF3 B 0xF0 VDCINADC 0xEF LCDSEGE2 0xED IPSME 0xEC ...
Page 24
ADE7566/ADE7569/ADE7166/ADE7169 Mnemonic Address LCDCLK 0x96 LCDCON 0x95 MDATH 0x94 MDATM 0x93 MDATL 0x92 MADDPT 0x91 P1 0x90 TH1 0x8D TH0 0x8C Details Mnemonic Table 82 TL1 Table 78 TL0 Table 30 TMOD Table 30 TCON Table 30 PCON Table 30 ...
Page 25
POWER MANAGEMENT The ADE7566/ADE7569/ADE7166/ADE7169 have elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. The Table 15. Power Management SFRs SFR Address R/W Mnemonic 0xEC R/W IPSME 0xF5 R/W BATPR 0xF8 R/W ...
Page 26
ADE7566/ADE7569/ADE7166/ADE7169 Table 17. Power Management Interrupt Flag SFR (IPSMF, 0xF8) Bit Address Mnemonic Default 7 0xFF FPSR 0 6 0xFE FPSM 0 5 0xFD FSAG 0 4 0xFC RESERVED 0 3 0xFB FVADC 0 2 0xFA FBAT 0 1 0xF9 ...
Page 27
Table 22. Scratch Pad 2 SFR (SCRATCH2, 0xFC) Bit Mnemonic Default Description SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 3 SFR ...
Page 28
ADE7566/ADE7569/ADE7166/ADE7169 POWER SUPPLY ARCHITECTURE Each ADE7566/ADE7569/ADE7166/ADE7169 has two power supply inputs, V and V , and require only a single 3 BAT power supply at V for full operation. A battery backup secondary power supply, with ...
Page 29
POWER SUPPLY MONITOR INTERRUPT (PSM) The power supply monitor interrupt (PSM) alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) ...
Page 30
ADE7566/ADE7569/ADE7166/ADE7169 Battery Switchover and Power Supply Restored PSM Interrupt The ADE7566/ADE7569/ADE7166/ADE7169 can be configured to generate a PSM interrupt when the source of V changes from indicating battery switchover. SWOUT DD BAT Setting the EBSO bit ...
Page 31
USING THE POWER SUPPLY FEATURES In an energy meter application, the 3.3 V power supply (V typically generated from the ac line voltage and regulated to 3 voltage regulator IC. The preregulated dc voltage, typically 5 V ...
Page 32
ADE7566/ADE7569/ADE7166/ADE7169 Table 26. Power Supply Event Timing Operating Modes Parameter Time Description min Time between when min Time between when Time between when V 3 switchover. t ...
Page 33
OPERATING MODES PSM0 (NORMAL MODE) In PSM0, normal operating mode, V SWOUT All of the analog circuitry and digital circuitry powered by V and V are enabled by default. In normal mode, the INTD INTA default clock frequency ...
Page 34
ADE7566/ADE7569/ADE7166/ADE7169 3.3 V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE7566/ADE7569/ADE7166/ADE7169 from PSM2. The events that can cause the ADE7566/ADE7569/ADE7166/ ADE7169 to wake up from PSM2 are listed in the wake-up Table ...
Page 35
TRANSITIONING BETWEEN OPERATING MODES The operating mode of the ADE7566/ADE7569/ADE7166/ ADE7169 is determined by the power supply connected Therefore, changes in the power supply, such as when SWOUT V switches from when V ...
Page 36
ADE7566/ADE7569/ADE7166/ADE7169 PSM0 NORMAL MODE V CONNECTED TO V SWOUT POWER SUPPLY RESTORED PSM1 AUTOMATIC BATTERY SWITCHOVER BATTERY MODE V CONNECTED TO V SWOUT DD POWER SUPPLY WAKE-UP RESTORED EVENT PSM2 SLEEP MODE V CONNECTED TO V SWOUT BAT Figure 37. ...
Page 37
ENERGY MEASUREMENT The ADE7566/ADE7569/ADE7166/ADE7169 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs ...
Page 38
ADE7566/ADE7569/ADE7166/ADE7169 Table 30. Energy Measurement SFRs Address R/W Name 0x91 R/W MADDPT 0x92 R/W MDATL 0x93 R/W MDATM 0x94 R/W MDATH 0xD1 R VRMSL 0xD2 R VRMSM 0xD3 R VRMSH 0xD4 R IRMSL 0xD5 R IRMSM 0xD6 R IRMSH 0xD9 ...
Page 39
I AP PGA1 I ADC HPF I N PGA1 ADC HPF I BP IBGAIN[11:0] PHCAL[7:0] Ф PGA2 ADC HPF V 2N Figure 39. ADE7166 and ADE7169 Energy Metering Block Diagram ADE7566/ADE7569/ADE7166/ADE7169 INTEGRATOR ...
Page 40
ADE7566/ADE7569/ADE7166/ADE7169 ENERGY MEASUREMENT REGISTERS Table 31. Energy Measurement Register List Address Mnemonic R/W Length MADDPT[6:0] (Bits) 0x00 Reserved 0x01 WATTHR R 24 0x02 RWATTHR R 24 0x03 LWATTHR R 24 0x04 VARHR 0x05 RVARHR R 24 ...
Page 41
Address Mnemonic R/W Length MADDPT[6:0] (Bits) 0x26 VADIV R/W 8 0x27 CF1NUM R/W 16 0x28 CF1DEN R/W 16 0x29 CF2NUM R/W 16 0x2A CF2DEN R/W 16 0x3B Reserved 0x3C Reserved 0x3D CALMODE 2 R/W 8 0x3E Reserved 0x3F Reserved 1 ...
Page 42
ADE7566/ADE7569/ADE7166/ADE7169 Bit Mnemonic Default 1 FREQSEL 0 WAVEN 0 1 This function is not available in the ADE7566 and ADE7166. Table 34. WAVMODE Register (0x0D) Bit Mnemonic Default WAV2SEL[2:0] 000 WAV1SEL[2:0] 000 1 to ...
Page 43
Bit Mnemonic Default VARNOLOAD[1: APNOLOAD[1: This function is not available in the ADE7566 and ADE7166. Table 36. ACCMODE Register (0x0F) Bit Mnemonic Default Description 1 7 ICHANNEL 0 This bit ...
Page 44
ADE7566/ADE7569/ADE7166/ADE7169 Bit Mnemonic Default Description PGA1[2:0] 000 These bits define the current channel input gain. PGA1[2:0] 000 001 010 011 100 1 This gain is not recommended in the ADE7166 and ADE7169 because it can create an ...
Page 45
Table 41. Interrupt Status 3 SFR (MIRQSTH, 0xDE) Bit Interrupt Flag Description 7 RESET Indicates the end of a reset (for both software and hardware reset). 6 Reserved. 5 WFSM Logic 1 indicates that new data is present in the ...
Page 46
ADE7566/ADE7569/ADE7166/ADE7169 Table 44. Interrupt Enable 3 SFR (MIRQENH, 0xDB) Bit Interrupt Enable Bit Description Reserved. 5 WFSM When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core. 4 PKI ...
Page 47
ANALOG-TO-DIGITAL CONVERSION Each ADE7566/ADE7569/ADE7166/ADE7169 has two sigma- delta (Σ-Δ) analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In ...
Page 48
ADE7566/ADE7569/ADE7166/ADE7169 Antialiasing Filter Figure 43 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal ...
Page 49
REFERENCE {GAIN[2:0 PGA1 PGA1 0.25V, 0.125V, 62.5mV, 31.3mV 0V ANALOG INPUT RANGE *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY ...
Page 50
ADE7566/ADE7569/ADE7166/ADE7169 Voltage Channel ADC Figure 47 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces ...
Page 51
Calibration Concerns Typically, when a meter is being calibrated, the voltage and current circuits are separated, as shown in Figure 48. This means that current passes through only the phase or neutral circuit. Figure 48 shows current being passed through ...
Page 52
ADE7566/ADE7569/ADE7166/ADE7169 –88.0 –88.5 –89.0 –89.5 –90.0 –90 FREQ FREQUENCY (Hz) Figure 51. Combined Phase Response of the Digital Integrator and Phase Compensator –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 –6 FREQUENCY ...
Page 53
POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7566/ADE7569/ADE7166/ADE7169 has a zero- crossing detection circuit on the voltage channel. This zero crossing is used to produce a zero-crossing internal signal (ZX) and is used in calibration mode. The zero-crossing is generated by ...
Page 54
ADE7566/ADE7569/ADE7166/ADE7169 Line Voltage SAG Detection In addition to detection of the loss of the line voltage signal (zero crossing), the ADE7566/ADE7569/ADE7166/ADE7169 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak ...
Page 55
PHASE COMPENSATION The ADE7566/ADE7569/ADE7166/ADE7169 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, ...
Page 56
ADE7566/ADE7569/ADE7166/ADE7169 Current Channel RMS Calculation Each ADE7566/ADE7569/ADE7166/ADE7169 simultaneously calculates the rms values for the current and voltage channels in different registers. Figure 61 shows the detail of the signal processing chain for the rms calculation on the current channel. The ...
Page 57
MODE 1[5] HPF I DIGITAL PA INTEGRATOR* dt HPF I PB IBGAIN Figure 61. ADE7166/ ADE7169 Current Channel RMS Signal Processing with PGA1 = VOLTAGE SIGNAL (V(t)) 0x28F5 0xD70B LPF1 VOLTAGE CHANNEL Figure 62. Voltage ...
Page 58
ADE7566/ADE7569/ADE7166/ADE7169 Voltage Channel RMS Calculation Figure 62 shows details of the signal processing chain for the rms calculation on the voltage channel. The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode ...
Page 59
Active Power Gain Calibration Figure 65 shows the signal processing chain for the active power calculation in the ADE7566/ADE7569/ADE7166/ADE7169. As explained previously, the active power is calculated by filtering the output of the multiplier with a low-pass filter. Note that ...
Page 60
ADE7566/ADE7569/ADE7166/ADE7169 ACTIVE ENERGY CALCULATION As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 13 where power ...
Page 61
Figure 66 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are ...
Page 62
ADE7566/ADE7569/ADE7166/ADE7169 ACTIVE ENERGY NO-LOAD THRESHOLD ACTIVE POWER NO-LOAD THRESHOLD APSIGN FLAG APNOLOAD POS INTERRUPT STATUS REGISTERS Figure 68. Energy Accumulation in Absolute Accumulation Mode Active Energy Pulse Output All of the ADE7566/ADE7569/ADE7166/ADE7169 circuitry has a pulse output whose frequency is ...
Page 63
When a new half-line cycle is written in the LINCYC register, the LWATTHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation ...
Page 64
ADE7566/ADE7569/ADE7166/ADE7169 Reactive Power Gain Calibration Figure 71 shows the signal processing chain for the ADE7569/ADE7169 reactive power calculation. As explained in the Reactive Power Calculation for the ADE7569/ADE7169 section, the reactive power is calculated by applying a low-pass filter to ...
Page 65
When SAVARM in the ACCMODE register (0x0F) is set, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added the reactive energy register. ...
Page 66
ADE7566/ADE7569/ADE7166/ADE7169 Integration Time Under Steady Load: Reactive Energy As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the ...
Page 67
VAR Absolute Accumulation Mode The ADE7569/ADE7169 are placed in absolute accumulation mode by setting the ABSVARM bit in the ACCMODE register (0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive power and ignoring ...
Page 68
ADE7566/ADE7569/ADE7166/ADE7169 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. V and I are the effective voltage and rms rms current delivered to the load, respectively. Therefore, the apparent power (AP) ...
Page 69
APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. = ∫ Apparent Energy Apparent Power The ADE7566/ADE7569/ADE7166/ADE7169 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in an ...
Page 70
ADE7566/ADE7569/ADE7166/ADE7169 Apparent Energy Pulse Output All the ADE7566/ADE7569/ADE7166/ADE7169 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also be ...
Page 71
ENERGY-TO-FREQUENCY CONVERSION The ADE7566/ADE7569/ADE7166/ADE7169 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. One convenient way to do this is for the manufacturer to provide ...
Page 72
ADE7566/ADE7569/ADE7166/ADE7169 ENERGY REGISTER SCALING The ADE7566/ADE7569/ADE7166/ADE7169 provide measurements of active, reactive, and apparent energies that use separate paths and filtering for calculation. The difference in data paths can result in small differences in LSB weight between active, reactive, and apparent ...
Page 73
TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS The ADE7566/ADE7569/ADE7166/ADE7169 include temperature measurements as well as battery and supply voltage measurements. These measurements enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external circuitry. The ...
Page 74
ADE7566/ADE7569/ADE7166/ADE7169 Table 49. Temperature and Supply Delta SFR (DIFFPROG, 0xF3) Bit Mnemonic Default Reserved TEMP_DIFF[2: VDCIN_DIFF[2:0] 0 Table 50. Start ADC Measurement SFR (ADCGO, 0xD8) Bit Address Mnemonic 7 ...
Page 75
TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE7566/ADE7569/ADE7166/ADE7169 includes a dedicated ADC. An 8-bit Temperature ADC Value SFR (TEMPADC, 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There are two ...
Page 76
ADE7566/ADE7569/ADE7166/ADE7169 To set up background battery measurements, follow these steps: 1. Configure the Battery Detection Threshold SFR (BATVTH, 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT in the Power Management Interrupt ...
Page 77
External Voltage ADC in PSM1 and PSM2 An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7566/ADE7569/ ADE7166/ADE7169. • In PSM0 operating mode, the 8052 is active. External voltage measurements are ...
Page 78
ADE7566/ADE7569/ADE7166/ADE7169 8052 MCU CORE ARCHITECTURE The ADE7566/ADE7569/ADE7166/ADE7169 have an 8052 MCU core and use the 8052 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and its ...
Page 79
Table 57. Program Control SFR (PCON, 0x87) Bit Default Description 7 0 SMOD bit. Double baud rate control Reserved. Should be left cleared. Table 58. Data Pointer Low SFR (DPL, 0x82) Bit Default Description 7 to ...
Page 80
ADE7566/ADE7569/ADE7166/ADE7169 BASIC 8052 REGISTERS Program Counter (PC) The program counter holds the two byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that ...
Page 81
STANDARD 8052 SFRS The standard 8052 special function registers include the Accumulator, B, PSW, DPTR, and SP SFRs described in the Basic 8052 Registers section. The standard 8052 SFRs also define timers, the serial port interface, interrupts, I/O ports, and ...
Page 82
ADE7566/ADE7569/ADE7166/ADE7169 Address 0x80 through Address 0xFF of general-purpose RAM are shared with the special function registers. The mode of addressing determines which memory space is accessed, as shown in Figure 83. 0xFF ACCESSIBLE BY ACCESSIBLE BY INDIRECT ADDRESSING DIRECT ADDRESSING ...
Page 83
Direct Addressing With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note that indirect or ...
Page 84
ADE7566/ADE7569/ADE7166/ADE7169 INSTRUCTION SET Table 64 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance. Table 64. Instruction Set Mnemonic Description ARITHMETIC ADD A,Rn ...
Page 85
Mnemonic Description RLC A Rotate A Left Through Carry Rotate A Right. RRC A Rotate A Right Through Carry. DATA TRANSFER MOV A,Rn Move Register to A. MOV A,@Ri Move Indirect Memory to A. MOV Rn,A Move A ...
Page 86
ADE7566/ADE7569/ADE7166/ADE7169 Mnemonic Description JNC rel Jump on Carry Equal rel Jump on Accumulator = 0. JNZ rel Jump on Accumulator Not Equal to 0. DJNZ Rn,rel Decrement Register, JNZ Relative. LJMP Long Jump Unconditional. LCALL addr16 Long ...
Page 87
SUBB A, Source This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. Affected Status Flags C Set if there is a borrow needed for Bit 7. Cleared otherwise. ...
Page 88
ADE7566/ADE7569/ADE7166/ADE7169 DUAL DATA POINTERS Each ADE7566/ADE7569/ADE7166/ADE7169 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the Data Pointer Control SFR (DPCON, 0xA7). DPCON features automatic hardware postincrement and postdecrement, as well as ...
Page 89
INTERRUPT SYSTEM The unique power management architecture of the ADE7566/ ADE7569/ADE7166/ADE7169 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A ...
Page 90
ADE7566/ADE7569/ADE7166/ADE7169 Table 69. Interrupt Priority SFR (IP, 0xB8) Bit Address Mnemonic 7 0xBF PADE 6 0xBE PTEMP 5 0xBD PT2 4 0xBC PS 3 0xBB PT1 2 0xBA PX1 1 0xB9 PT0 0 0xB8 PX0 Table 70. Interrupt Enable and ...
Page 91
INTERRUPT FLAGS The interrupt flags and status flags associated with the interrupt vectors are shown in Table 72 and Table 73. Most of the interrupts have flags associated with them. Table 72. Interrupt Flags Interrupt Source Flag IE0 TCON.1 TF0 ...
Page 92
ADE7566/ADE7569/ADE7166/ADE7169 IPSMF FPSM PSM (IPSMF.6) IPSME MIDNIGHT RTC ALARM MIRQSTH MIRQSTM MIRQSTL ADE MIRQENH MIRQENM MIRQENL WATCHDOG TIMEOUT WATCHDOG WDIR TEMPADC INTERRUPT TEMP ADC IT0 0 INT0 EXTERNAL INTERRUPT 0 1 TF0 TIMER 0 IT1 0 EXTERNAL INT1 INTERRUPT 1 ...
Page 93
INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the ...
Page 94
ADE7566/ADE7569/ADE7166/ADE7169 WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7566/ADE7569/ ADE7166/ADE7169 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by ...
Page 95
Table 76. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) Bit Mnemonic Default 7 WDPROT_PROTKY7 PROTKY[7:0] 0xFF Writing to the Watchdog Timer SFR (WDCON, 0xC0) Writing data to the WDCON SFR involves a ...
Page 96
ADE7566/ADE7569/ADE7166/ADE7169 LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7566/ADE7569/ADE7166/ADE7169 functions capable of driving LCDs with 2×, 3×, and 4× multiplexing. The ...
Page 97
Table 79. LCD Configuration X SFR (LCDCONX, 0x9C) Bit Mnemonic Default 7 Reserved 0 6 EXTRES BIASLVL[5:0] 0 Table 80. LCD Bias Voltage When Contrast Control Is Enabled BIASLVL[ BLVL ...
Page 98
ADE7566/ADE7569/ADE7166/ADE7169 Table 83. LCD Frame Rate Selection for f FD3 FD2 FD1 FD0 f (Hz) LCD 256 170 128 102 ...
Page 99
Table 86. LCD Pointer SFR (LCDPTR, 0xAC) Bit Mnemonic Default 7 R RESERVED ADDRESS 0 Table 87. LCD Data SFR (LCDDAT, 0xAE) Bit Mnemonic Default LCDDATA 0 Table 88. LCD Segment ...
Page 100
ADE7566/ADE7569/ADE7166/ADE7169 BLINK MODE Blink mode is enabled by setting the BLINKEN bit in the LCD Configuration SFR (LCDCON, 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD screen appears ...
Page 101
VOLTAGE GENERATION The ADE7566/ADE7569/ADE7166/ADE7169 provide two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V ADE7566/ADE7569/ADE7166/ ADE7169. There is ...
Page 102
ADE7566/ADE7569/ADE7166/ADE7169 Table 90. Bits Controlling LCD Functionality in PSM2 Mode LCDPSM2 LCDEN Result 0 0 The display is off in PSM2 The display PSM2 The display is off in PSM2. In addition, note ...
Page 103
FLASH MEMORY OVERVIEW Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default state of a byte of flash memory is 0xFF (erased). When a byte of flash memory is programmed, the required bits change from ...
Page 104
ADE7566/ADE7569/ADE7166/ADE7169 FLASH MEMORY ORGANIZATION The flash memory provided by the ADE7566/ADE7569/ ADE7166/ADE7169 are segmented into 32 pages of 512 bytes each the user to decide which flash memory to allocate for data memory. ...
Page 105
ECON—Flash/EE Memory Control SFR Programming flash memory is done through the Flash Control SFR (ECON, 0xB9). This SFR allows the user to read, write, erase, or verify the flash memory method of security, a key ...
Page 106
ADE7566/ADE7569/ADE7166/ADE7169 Table 98. Flash Read Protection SFR (PROTR, 0xBF) Bit Mnemonic Default Description PROTR 0xFF This SFR is used to write the read protection bits for Page 0 to Page 31 of the flash memory (see the ...
Page 107
PROTECTING THE FLASH MEMORY Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected are not able to be read by the end user. ...
Page 108
ADE7566/ADE7569/ADE7166/ADE7169 Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use some reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate ...
Page 109
TIMERS Each ADE7566/ADE7569/ADE7166/ADE7169 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/ Counter 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter con- sists of ...
Page 110
ADE7566/ADE7569/ADE7166/ADE7169 Table 104. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88) Bit Address Mnemonic Default 7 0x8F TF1 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0x8B IE1 0 2 0x8A IT1 ...
Page 111
Table 106. Timer 0 High Byte SFR (TH0, 0x8C) Bit Mnemonic Default Description TH0 0 Timer 0 Data High Byte. Table 107. Timer 0 Low Byte SFR (TL0, 0x8A) Bit Mnemonic Default Description TL0 ...
Page 112
ADE7566/ADE7569/ADE7166/ADE7169 Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 97. Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents ...
Page 113
CORE P1.4/T2 CONTROL TR2 RELOAD TRANSITION DETECTOR P1.3/ T2EX CONTROL EXEN2 Figure 99. Timer/Counter 2, 16-Bit Autoreload Mode f CORE P1.4/T2 CONTROL TR2 ...
Page 114
ADE7566/ADE7569/ADE7166/ADE7169 PLL The ADE7566/ADE7569/ADE7166/ADE7169 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency ...
Page 115
Table 117. Peripheral Configuration SFR (PERIPH, 0xF4) Bit Mnemonic Default 7 RXFLAG 0 6 VSWSOURCE 1 5 VDD_OK 1 4 PLL_FLT 0 3 REF_BAT_EN 0 2 Reserved RXPROG[1:0] 00 Table 118. Start ADC Measurement SFR (ADCGO, ...
Page 116
ADE7566/ADE7569/ADE7166/ADE7169 REAL-TIME CLOCK The ADE7566/ADE7569/ADE7166/ADE7169 have an embedded real-time clock (RTC) as shown in external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in ...
Page 117
Table 120. RTC Configuration SFR (TIMECON, 0xA1) Bit Mnemonic Default Description 7 MIDNIGHT 0 Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event ...
Page 118
ADE7566/ADE7569/ADE7166/ADE7169 Table 125. Alarm Interval SFR (INTVAL, 0xA6) Bit Mnemonic Default Description INTVAL 0 The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the ...
Page 119
READ AND WRITE OPERATIONS Writing to the RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, Hundredths of a Second Counter SFR (HTHSEC, 0xA2), Seconds Counter SFR (SEC, 0xA3), Minutes Counter SFR (MIN, 0xA4), and ...
Page 120
ADE7566/ADE7569/ADE7166/ADE7169 Take care when changing the interval timer time base. The recommended procedure is as follows the Alarm Interval SFR (INTVAL, 0xA6) is going to be modified, write to this register first. Then, wait for one 128 Hz ...
Page 121
UART SERIAL INTERFACE The ADE7566/ADE7569/ADE7166/ADE7169 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at f • ...
Page 122
ADE7566/ADE7569/ADE7166/ADE7169 Table 133. Serial Port Buffer SFR (SBUF, 0x99) Bit Mnemonic SBUF Table 134. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) Bit Mnemonic Default 7 OWE SBTH1, ...
Page 123
Table 136. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock Ideal Baud CD 115,200 0 115,200 1 57,600 0 57,600 1 38,400 0 38,400 1 38,400 2 19,200 0 19,200 1 19,200 2 19,200 3 9600 ...
Page 124
ADE7566/ADE7569/ADE7166/ADE7169 UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at f Mode 0 is selected when the SM0 and SM1 bits in the Serial Communications Control Register Bit Description SFR (SCON, 0x98) are cleared. In this shift ...
Page 125
To transmit, the eight data bits must be written into the Serial Port Buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). When transmission is initiated, ...
Page 126
ADE7566/ADE7569/ADE7166/ADE7169 Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8). The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 ...
Page 127
SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: ⎛ f ⎜ = × CORE SBAUDF 64 ⎜ + × × DIV SBTH 16 ...
Page 128
ADE7566/ADE7569/ADE7166/ADE7169 SERIAL PERIPHERAL INTERFACE (SPI) The ADE7566/ADE7569/ADE7166/ADE7169 integrate a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that eight bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users ...
Page 129
Table 140. SPI Configuration SFR 1 (SPIMOD1, 0xE8) Bit Address Mnemonic Default 0xEF to Reserved 0 0xEE 5 0xED INTMOD 0 4 0xEC AUTO_SS 1 3 0xEB SS_EN 0 2 0xEA RxOFW 0xE9 ...
Page 130
ADE7566/ADE7569/ADE7166/ADE7169 Table 141. SPI Configuration SFR 2 (SPIMOD2, 0xE9) Bit Mnemonic Default Description 7 SPICONT 0 Master Mode, SPI Continuous Transfer Mode Enable Bit. SPICONT SPIEN 0 SPI Interface Enable Bit. SPIEN SPIODO 0 ...
Page 131
Table 142. SPI Interrupt Status SFR (SPISTAT, 0xEA) Bit Mnemonic Default Description 7 BUSY 0 SPI Peripheral Busy Flag. BUSY MMERR 0 SPI Multimaster Error Flag. MMERR SPIRxOF 0 SPI Receive Overflow Error Flag. ...
Page 132
ADE7566/ADE7569/ADE7166/ADE7169 SS (Slave Select Pin) In SPI slave mode, a transfer is initiated by the assertion of low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS according to the ...
Page 133
SPI INTERRUPT AND STATUS FLAGS The SPI interface has several status flags that indicate the status of the double-buffered receive and transmit registers. Figure 109 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the ...
Page 134
ADE7566/ADE7569/ADE7166/ADE7169 COMPATIBLE INTERFACE The ADE7566/ADE7569/ADE7166/ADE7169 support a fully 2 2 licensed I C interface. The I C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. ...
Page 135
Table 147 Interrupt Status Register SFR (SPI2CSTAT, 0xEA) Bit Mnemonic Default 7 I2CBUSY 0 6 I2CNOACK 0 5 I2CRxIRQ 0 4 I2CTxIRQ I2CFIFOSTAT[1: I2CACC_ERR 0 0 I2CTxWR_ERR 0 READ AND WRITE ...
Page 136
ADE7566/ADE7569/ADE7166/ADE7169 RECEIVE AND TRANSMIT FIFOS 2 The I C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with 2 using the I C peripheral. Figure 113 shows the ...
Page 137
I/O PORTS PARALLEL I/O The ADE7566/ADE7569/ADE7166/ADE7169 use three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on-chip. In general, ...
Page 138
ADE7566/ADE7569/ADE7166/ADE7169 I/O REGISTERS Table 149. Extended Port Configuration SFR (EPCFG, 0x9F) Bit Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_FP23 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 150. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2) Bit ...
Page 139
Table 153. Port 0 SFR (P0, 0x80) Bit Address Mnemonic 7 0x87 T1 6 0x86 T0 5 0x85 4 0x84 3 0x83 CF2 2 0x82 CF1 1 0x81 0 0x80 INT1 1 When an alternate function is chosen for a ...
Page 140
ADE7566/ADE7569/ADE7166/ADE7169 Table 156. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL External Battery Control Input INT1 External Interrupt INT1 Wake-up from PSM2 Operating Mode P0.1 FP19 LCD Segment Pin P0.2 CF1 ADE Calibration Frequency Output P0.3 CF2 ADE ...
Page 141
PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2); they are enabled by default. The ...
Page 142
ADE7566/ADE7569/ADE7166/ADE7169 DETERMINING THE VERSION OF THE ADE7566/ADE7569 Each ADE7566/ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7566/ADE756 version corresponding to ...
Page 143
OUTLINE DIMENSIONS 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ADE7566/ADE7569/ADE7166/ADE7169 0.75 0.60 1.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° 16 0° ...
Page 144
... ADE7566/ADE7569/ADE7166/ADE7169 ORDERING GUIDE Anti- 1 Model Tamper 2 ADE7566ACPZF8 No ADE7566ACPZF8- ADE7566ACPZF16 No 2 ADE7566ACPZF16- ADE7566ASTZF8 No 2 ADE7566ASTZF8- ADE7566ASTZF16 No 2 ADE7566ASTZF16- ADE7569ACPZF16 No 2 ADE7569ACPZF16- ADE7569ASTZF16 No 2 ADE7569ASTZF16- ADE7166ACPZF8 Yes 2 ADE7166ACPZF8-RL Yes 2 ADE7166ACPZF16 Yes 2 ADE7166ACPZF16-RL Yes ADE7166ASTZF8 2 Yes 2 ADE7166ASTZF8-RL Yes 2 ADE7166ASTZF16 Yes 2 ADE7166ASTZF16-RL Yes ADE7169ACPZF16 2 Yes ...