Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 73

• Manufacturer Part Number: Z9025106PSC
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8
Infrared Interface
The Z90255 supports the Infrared (IR) Remote Control interface with a minimum
of software overhead.
Two bytes of data are received through the Infrared (IR) Interface. The lower
byte, bits 7-0, is stored in IR Capture Register 0. The upper byte, bits 15-8, is
stored in IR Capture Register 1.
When an IR interrupt occurs, the IR capture registers contain the amount of time
passed from the previous IR interrupt if bit 0 in the TCR0 is set to 0. If bit 0 is set
to 1, the IR capture registers contain the amount of time passed from the last
overflow of the IR capture counter. The IR interrupt flags are reset by the IR
interrupt service routine software. Refer to Table 50 through Table 53.
Timer Control Register 0
Rising edge (falling edge) interrupt is preserved even when a falling edge (rising
edge) interrupt occurs. But it is overridden by a second rising edge (falling edge) if
the second one occurs before the first rising edge (falling edge) is serviced.
Preservation of the interrupt means that it generates the hardware interrupt after
the first interrupt is serviced when two different (rising edge/falling edge) interrupts
are already ON.
Table 50 Timer Control Register 0 01h: Bank C (TCR0)
Bit/
Field
P62 I/O
definition
P61 I/O
definition
P60 I/O
definition
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Bit
Position
2
1
0
R/W
7
x
R/W
6
x
R/W
R/W
R/W
R/W
R/W
5
x
Value Description
0
1
0
1
0
1
32 KB Television Controller with OSD
R/W
Data Output
Data Input - POR
Data Output
Data Input - POR
Data Output
Data Input - POR
4
x
R/W
3
x
R/W
2
x
R/W
PS001301-0800
1
x
R/W
0
x
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