CY7C64714-56LFXC Cypress Semiconductor Corp, CY7C64714-56LFXC Datasheet - Page 38

• Manufacturer Part Number: CY7C64714-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64714-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.10
Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
10.11
Table 10-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Table 10-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is that the set-
up time t
Document #: 38-08039 Rev. *C
t
t
t
t
t
t
t
t
t
t
t
t
t
WRpwl
WRpwh
SFD
FDH
XFD
IFCLK
SPE
PEH
XFLG
IFCLK
SPE
PEH
XFLG
Parameter
Parameter
Parameter
SPE
Slave FIFO Asynchronous Write
Slave FIFO Synchronous Packet End Strobe
and the hold time t
SLWR Pulse LOW
SLWR Pulse HIGH
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
SLWR to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Figure 10-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram
SLWR/SLCS#
Figure 10-10. Slave FIFO Asynchronous Write Timing Diagram
PEH
PKTEND
FLAGS
DATA
FLAGS
IFCLK
for PKTEND must be met.
Description
Description
Description
t
WRpwl
t
SFD
t
XFD
t
FDH
t
SPE
Although typically there are no specific timing requirements for
asserting PKTEND in relation to SLWR, there exists a specific
corner case condition that needs attention. While using the
PKTEND to commit a one byte/word packet, an additional
timing requirement needs to be met when the FIFO is
t
WRpwh
t
PEH
t
XFLG
20.83
20.83
Min.
Min.
14.6
Min.
8.6
2.5
50
70
10
10
0
[20]
[17]
Max.
Max.
Max.
13.5
200
9.5
70
[17]
CY7C64713/14
[19]
[19]
Page 38 of 50
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns