CY7C66113C-LFXCT Cypress Semiconductor Corp, CY7C66113C-LFXCT Datasheet - Page 23

• Manufacturer Part Number: CY7C66113C-LFXCT
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

I
Bits [7..0]: I
Contains 8-bit data on the I
I
The I
Table 9. I
Document Number: 38-08024 Rev. *D
2
2
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
C Data
C Status and Control
Bit
0
1
2
3
4
5
6
7
2
C Status and Control register bits are defined in
2
I
Received Stop
ARB Lost/Restart
Addr
ACK
Xmit Mode
Continue/Busy
MSTR Mode
C Status and Control Register Bit Definitions
2
2
C Enable
C Data
7
X
7
MSTR Mode Continue/Bu
R/W
0
R/W
I
2
C Data 7
Name
2
C Bus.
6
R/W
X
6
sy
R/W
0
I
2
When set to ‘1’, the I
normally.
Reads 1 only in slave receive mode, when I
last transaction).
Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
Write to 1 for transmit mode, 0 for receive mode.
Write 1 to indicate ready for next transaction.
Reads 1 when I
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
C Data 6
Figure 27. I
5
R/W
X
5
Xmit Mode
R/W
0
I
2
C Data 5
2
C compatible block is busy with a transaction, 0 when transaction is complete.
Figure 26. I
2
C compatible function is enabled. When cleared, I
Table
2
C Status and Control Register
4
ACK
R/W
0
4
R/W
X
I
2
9, with a more detailed description following.
C Data 4
2
C Data Register
3
Addr
R/W
0
3
R/W
X
I
Description
2
2
C Stop bit detected (unless firmware did not ACK the
C Data 3
CY7C66013C, CY7C66113C
2
ARB
Lost/Restart
R/W
0
2
R/W
X
I
2
C Data 2
2
1
X
1
Received
Stop
R/W
0
R/W
I
C GPIO pins operate
2
C Data 1
ADDRESS 0x29
ADDRESS 0x28
0
I
R/W
0
0
R/W
X
Page 23 of 59
2
I
2
C Enable
C Data 0
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