PIC12F629T-I/SN Microchip Technology, PIC12F629T-I/SN Datasheet
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... Microchip Technology Inc. PIC12F629/675 Data Sheet 8-Pin FLASH-Based 8-Bit CMOS Microcontrollers DS41190C ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... PIC12F675 1024 * 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. 2003 Microchip Technology Inc. PIC12F629/675 Low Power Features: • Standby Current 2.0V, typical • Operating Current: - 8.5 µ ...
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... PIC12F629/675 Pin Diagrams 8-pin PDIP, SOIC, DFN-S GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/V GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41190C-page GP0/CIN+/ICSPDAT 2 7 GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/V REF GP2/AN2/T0CKI/INT/COUT /ICSPCLK 2003 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2003 Microchip Technology Inc. ® Devices ...................................................................................................................... 122 PIC12F629/675 ...
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... PIC12F629/675 NOTES: DS41190C-page 4 2003 Microchip Technology Inc. ...
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... V REF AN0 AN1 AN2 AN3 Note 1: Higher order bits are from STATUS register. 2003 Microchip Technology Inc. PIC12F629/675 Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC12F629 and PIC12F675 devices are covered by this Data Sheet ...
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... Bi-directional I/O w/ programmable pull-up and interrupt-on-change AN A/D Channel 3 input ST TMR1 gate XTAL Crystal/resonator CMOS F OSC /4 output TTL CMOS Bi-directional I/O w/ programmable pull-up and interrupt-on-change ST TMR1 clock XTAL Crystal/resonator ST External clock input/RC oscillator connection Power Ground reference Power Positive supply Description 2003 Microchip Technology Inc. ...
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... Stack Level 8 RESET Vector Interrupt Vector On-chip Program Memory 2003 Microchip Technology Inc. 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose regis- ters and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank ...
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... General Purpose accesses Registers 20h-5Fh 64 Bytes 5Fh 60h 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. 1: Not a physical register. 2: PIC12F675 only. 2003 Microchip Technology Inc. File Address (1) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah ...
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... Legend: — = unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’. 3: PIC12F675 only. 2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 (2) ...
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... WPU1 WPU0 --11 -111 IOC1 IOC0 --00 0000 — — VR1 VR0 0-0- 0000 0000 0000 -000 0000 WR RD ---- x000 ---- ---- xxxx xxxx ANS1 ANS0 44,59 -000 1111 2003 Microchip Technology Inc — — — — — 16 — 16 — — — — — ...
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... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the “ ...
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... PSA bit to ‘1’ (OPTION<3>). See Section 4.4. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and should be initialized before clearing T0IF bit. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 U-0 R/W-0 U-0 CMIE — — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared 2003 Microchip Technology Inc. U-0 R/W-0 TMR1IE — bit Bit is unknown ...
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... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... CAL3 CAL2 CAL1 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 R/W-0 R/W-x — POR BOD bit Bit is unknown R/W-0 U-0 U-0 CAL0 — — bit Bit is unknown 2003 Microchip Technology Inc. ...
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... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note “Implementing a Table Read" (AN556). 2003 Microchip Technology Inc. PIC12F629/675 2.3.2 STACK The PIC12F629/675 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1) ...
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... Not Used Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing ( FSR Register Location Select 1FFh 2003 Microchip Technology Inc. ...
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... Port pin is > Port pin is <V Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. Note: The ANSEL (9Fh) and CMCON (19h) ...
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... WPU5 WPU4 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W-x R/W-x TRISIO2 TRISIO1 TRISIO0 bit Bit is unknown R/W-1 R/W-1 R/W-1 WPU2 WPU1 WPU0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of GPIO ...
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... FIGURE 3-1: BLOCK DIAGRAM OF GP0 AND GP1 PINS Analog Data Bus Input Mode WPU GPPU RD WPU PORT TRISIO Analog Input Mode RD TRISIO RD PORT IOC EN RD IOC Interrupt-on-Change RD PORT To Comparator To A/D Converter 2003 Microchip Technology Inc Weak V DD I/O pin V SS ...
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... IOC Q EN Interrupt-on-Change RD PORT To TMR0 To INT To A/D Converter 2003 Microchip Technology Inc. 3.3.4 GP3/MCLR/V Figure 3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: ...
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... IOC Interrupt-on-Change To TMR1 or CLKGEN Note 1: Timer1 LP Oscillator enabled 2: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed. BLOCK DIAGRAM OF GP5 INTOSC Mode (1) TMR1LPEN V DD Weak GPPU Oscillator Circuit OSC2 V DD I/O pin V SS INTOSC Mode ( PORT 2003 Microchip Technology Inc. ...
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... WPU — — 96h IOC — — 9Fh ANSEL — ADCS2 Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by GPIO. 2003 Microchip Technology Inc. PIC12F629/675 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GP5 GP4 GP3 GP2 GP1 T0IE ...
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... PIC12F629/675 NOTES: DS41190C-page 26 2003 Microchip Technology Inc. ...
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... PSA Watchdog Timer WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register. 2003 Microchip Technology Inc. PIC12F629/675 Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined ...
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... PIC12F675. R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared OSC R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... OPTION_REG GPPU INTEDG 85h TRISIO — — Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. 2003 Microchip Technology Inc. PIC12F629/675 EXAMPLE 4-1: bcf STATUS,RP0 clrwdt clrf TMR0 bsf STATUS,RP0 movlw b’ ...
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... Timer1 module. Note: Additional information on timer modules is available in the PICmicro Reference Manual, (DS33023). 0 TMR1L 1 T1SYNC 1 Prescaler OSC /4 Internal 0 Clock 2 T1CKPS<1:0> TMR1CS TM Mid-Range TMR1ON TMR1GE T1G TMR1ON TMR1GE Synchronized Clock Input Synchronize Detect SLEEP Input 2003 Microchip Technology Inc. ...
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... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2003 Microchip Technology Inc. PIC12F629/675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...
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... Stops Timer1 Legend Readable bit - n = Value at POR DS41190C-page 32 R/W-0 R/W-0 R/W-0 OSC / Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown 2003 Microchip Technology Inc. ...
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... PIE1 EEIE ADIE Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2003 Microchip Technology Inc. 5.5 Timer1 Oscillator A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated kHz ...
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... PIC12F629/675 NOTES: DS41190C-page 34 2003 Microchip Technology Inc. ...
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... Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator ...
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... Table 6-1. DS41190C-page 36 TABLE 6-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions less > < > < FIGURE 6- Output Note: CINV bit (CMCON<4>) is clear. CINV COUT SINGLE COMPARATOR + Output – 2003 Microchip Technology Inc. ...
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... GP2/COUT Analog Input, ports always reads ‘0’ Digital Input CIS = Comparator Input Switch (CMCON<3>) 2003 Microchip Technology Inc. Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 12.0. Note: Comparator interrupts should be disabled during a Comparator mode change ...
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... TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified CINV CMCON EN RESET impedance of 10 kΩ GP0/CIN+ GP1/CIN- CV REF CM2:CM0 2003 Microchip Technology Inc. ...
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... To minimize power consumption while in SLEEP mode, turn off the comparator, CM2:CM0 = 111, and voltage reference, VRCON<7> 2003 Microchip Technology Inc. PIC12F629/675 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range): CV ...
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... Value on Value on Bit 0 all other POR, BOD RESETS 0000 0000 0000 000u GPIF 00-- 0--0 00-- 0--0 — TMR1IF -0-0 0000 -0-0 0000 CM0 00-- 0--0 00-- 0--0 — TMR1IE --11 1111 --11 1111 0-0- 0000 0-0- 0000 VR1 VR0 2003 Microchip Technology Inc. ...
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... DD is used analog voltage applied to V REF is used. The VCFG bit (ADCON0<6>) 2003 Microchip Technology Inc. PIC12F629/675 The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference ...
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... ADRESL LSB Bit 0 Unimplemented: Read as ‘0’ LSB Bit 0 10-bit A/D Result 2003 Microchip Technology Inc. ...
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... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion STATUS bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC12F629/675 U-0 U-0 R/W-0 R/W-0 — — CHS1 ...
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... Legend Readable bit - n = Value at POR DS41190C-page 44 R/W-0 R/W-0 R/W-1 ADCS1 ADCS0 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
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... IC = interconnect resistance SS = sampling switch C HOLD = sample/hold capacitance (from DAC) 2003 Microchip Technology Inc. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate Equation 7-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). ...
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... GPIO0 0000 0000 0000 000u INTF GPIF 00-- 0--0 00-- 0--0 — TMR1IF xxxx xxxx uuuu uuuu 00-- 0000 00-- 0000 GO ADON --11 1111 --11 1111 00-- 0--0 00-- 0--0 — TMR1IE xxxx xxxx uuuu uuuu -000 1111 -000 1111 ANS1 ANS0 2003 Microchip Technology Inc. ...
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... EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC12F629/675 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
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... Data EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown 2003 Microchip Technology Inc. ...
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... WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. 2003 Microchip Technology Inc. PIC12F629/675 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...
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... Bit 4 Bit 3 Bit 2 — — CMIF — — — WRERR WREN Value on all Value on Bit 1 Bit 0 other POR, BOD RESETS — TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ---- 2003 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • SLEEP • Code protection • ID Locations • In-Circuit Serial Programming 2003 Microchip Technology Inc. PIC12F629/675 The PIC12F629/675 has a Watchdog Timer that is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up ...
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... Specification for more information. R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 (1) (2) (4) ( Writable bit U = Unimplemented bit, read as ‘0’ bit is set 0 = bit is cleared R/P-1 R/P-1 R/P-1 R/P-1 bit bit is unknown 2003 Microchip Technology Inc. ...
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... C1 and C2 series resistor may be required for AT strip cut crystals varies with the Oscillator mode selected (Approx. value = 10 MΩ). 2003 Microchip Technology Inc. FIGURE 9-2: Clock from External System Open Note 1: Functions as GP4 in EC Osc mode. TABLE 9-1: ...
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... OSCILLATOR Z Section 12.0, for information OSC /4. Calibrating the Internal Oscillator CALIBRATING THE INTERNAL OSCILLATOR STATUS, RP0 ;Bank 1 3FFh ;Get the cal value OSCCAL ;Calibrate STATUS, RP0 ;Bank 0 OSC /4) is output on the OSC /4 can be used for test 2003 Microchip Technology Inc ...
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... Ripple Counter RC OSC Note 1: This is a separate oscillator from the INTOSC/EC oscillator. 2003 Microchip Technology Inc. PIC12F629/675 They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 9-4 ...
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... OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP BOD (see declines 2003 Microchip Technology Inc. ...
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... Table 9-6 shows the RESET conditions for some special registers, while Table 9-7 shows the RESET conditions for all the registers. 2003 Microchip Technology Inc. On any RESET (Power-on, Brown-out, Watchdog, etc.), the chip will remain in RESET until V above BV DD (see Figure 9-6) ...
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... Wake-up from SLEEP PWRTE = 1 1024•T OSC 1024•T OSC — — Value on all Value on Bit 0 other POR, BOD (1) RESETS 0001 1xxx 000q quuu C ---- --0x ---- --uq BOD PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu 2003 Microchip Technology Inc. ...
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... Comparator input changing, bit Timer1 rolling over, bit All other interrupts generating a wake-up will cause these bits RESET was due to brown-out, then bit All other RESETS will cause bit 2003 Microchip Technology Inc. • MCLR Reset during normal operation • MCLR Reset during SLEEP • ...
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... MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET DS41190C-page 60 T PWRT T OST T PWRT T OST DD T PWRT T OST 2003 Microchip Technology Inc. ): CASE CASE ...
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... Figure 9-11). The latency is the same for one or two- cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The 2003 Microchip Technology Inc. interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. ...
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... IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE (1) ADIF ADIE EEIF EEIE Note 1: PIC12F675 only. DS41190C-page 62 T0IF Wake-up (If in SLEEP mode) T0IE INTF INTE GPIF GPIE PEIE GIE 2003 Microchip Technology Inc. Interrupt to CPU ...
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... Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2003 Microchip Technology Inc. 9.4.2 TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON< ...
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... WDT time-out occurs. Value on all Value on Bit 0 other POR, BOD RESETS GPIF 0000 0000 0000 000u TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0 instruction). During normal SLEEP instructions clear the WDT SLEEP DD = Min., Temperature = Max., Max. 2003 Microchip Technology Inc. ...
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... SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 81h OPTION_REG GPPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer. 2003 Microchip Technology Inc. PIC12F629/675 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA ...
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... OST Interrupt Latency (Note 2) Processor in SLEEP PC+2 PC Inst( Dummy cycle Inst( instruction is being executed, the instruction. If the GIE bit is SLEEP is not desirable, the user SLEEP after the SLEEP instruction. 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) 2003 Microchip Technology Inc. ...
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... For complete details of serial programming, please refer to the Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure 9-14. 2003 Microchip Technology Inc. PIC12F629/675 FIGURE 9-14: not been External ...
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... PIC12F629/675 NOTES: DS41190C-page 68 2003 Microchip Technology Inc. ...
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... A read operation is performed on a register even if the instruction writes to that register. 2003 Microchip Technology Inc. PIC12F629/675 For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO ...
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... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ™ Mid-Range MCU 2003 Microchip Technology Inc. ...
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... Operation: Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2003 Microchip Technology Inc. PIC12F629/675 BCF Bit Clear f Syntax: [label] BCF f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ → ...
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... the result is stored back in register 'f'. DECF Decrement f Syntax: [label] DECF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register 'f the result is stored in the W register the result is stored back in register 'f'. 2003 Microchip Technology Inc. ...
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... Operation: Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'. 2003 Microchip Technology Inc. PIC12F629/675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → ...
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... Return with Literal label ] RETLW k 0 ≤ k ≤ 255 k → (W); TOS → PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2003 Microchip Technology Inc. ...
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... The contents of register 'f' are rotated one bit to the right through the Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f 2003 Microchip Technology Inc. PIC12F629/675 SLEEP Syntax: [ label ] SLEEP Operands: None 00h → WDT, Operation: 0 → ...
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... Exclusive OR W with f Syntax: [label] XORWF 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (W) .XOR. (f) → (destination) Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2003 Microchip Technology Inc. f,d ...
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... OQ - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2003 Microchip Technology Inc. PIC12F629/675 11.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
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... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP routines. 2003 Microchip Technology Inc. software ...
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... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. PIC12F629/675 11.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...
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... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion. 2003 Microchip Technology Inc. ...
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... Tricks for 8-pin FLASH PIC Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices. 2003 Microchip Technology Inc. PIC12F629/675 11.22 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
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... PIC12F629/675 NOTES: DS41190C-page 82 2003 Microchip Technology Inc. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, Ω a series resistor of 50-100 this pin directly 2003 Microchip Technology Inc. SS ........................................................................... -0. )...............................................................................................................± ).........................................................................................................± ∑ I DIS = V DD ...
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... FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41190C-page Frequency (MHz Frequency (MHz 2003 Microchip Technology Inc. ...
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... FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2003 Microchip Technology Inc. PIC12F629/675 Frequency (MHz) 20 DS41190C-page 85 ...
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... See section on Power-on Reset for details 0.05* — — V/ms See section on Power-on Reset for details — 2.1 — V can be lowered in SLEEP mode without losing RAM data. ≤ +85°C for industrial A ≤ +125°C for extended A Conditions < MHz: Z < F OSC < MHz 2003 Microchip Technology Inc. ...
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... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ...
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... and the additional current consumed when this Conditions Note WDT, BOD, Comparators, V REF , and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV REF Current ( Current (1) A/D Current 2003 Microchip Technology Inc. ...
Page 91
... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ...
Page 92
... and the additional current consumed when this ≤ +125°C for extended Conditions Note WDT, BOD, Comparators, V REF , and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV REF Current ( Current (1) A/D Current 2003 Microchip Technology Inc. ...
Page 93
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40° ...
Page 94
... In XT, HS and LP modes when external clock is used to drive OSC1 pF ≤ +85°C A ≤ +125° Using EECON to read/write V MIN = Minimum operating voltage ms are violated ≤ +85°C A ≤ +85°C A ≤ +125°C A MIN Minimum operating voltage V ms are violated 2003 Microchip Technology Inc. ...
Page 95
... MCLR Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Pin 464Ω for all pins 15 pF for OSC2 output 2003 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid ...
Page 96
... INTOSC mode ns RC Osc mode ns XT Osc mode ns HS Osc mode 4/F OSC µs LP oscillator, T OSC L/H duty cycle ns HS oscillator, T OSC L/H duty cycle ns XT oscillator, T OSC L/H duty cycle ns LP oscillator ns XT oscillator ns HS oscillator 2003 Microchip Technology Inc. ...
Page 97
... SLEEP start-up time* * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. PIC12F629/675 Freq Min Typ† ...
Page 98
... T CY — OSC New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150 * ns 300 ns — ns — — ns — 2003 Microchip Technology Inc. ...
Page 99
... Watchdog Timer Reset I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) RESET (due to BOD) Note delay only if PWRTE bit in configuration word is programmed to ‘0’. 2003 Microchip Technology Inc. PIC12F629/675 (Device not in Brown-out Detect time-out 34 DS41190C-page 97 ...
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... TBD ms Extended Temperature µs — — 2.0 2.025 — 2.175 V TBD — — — µs 100* — — 2003 Microchip Technology Inc. Conditions = 5V, -40°C to +85°C = 5V, -40°C to +85°C = OSC1 period = 5V, -40°C to +85°C ≤ B VDD (D005) ...
Page 101
... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. PIC12F629/675 ...
Page 102
... LSb DD — /32 — LSb ± 1/2 — — LSb ± 1/2* — — LSb — 2k* — — — 10* Comments V Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0) Ω µs 2003 Microchip Technology Inc. ...
Page 103
... Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module REF current is from External V 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2003 Microchip Technology Inc. Min Typ† Max Units — ...
Page 104
... LSb (i.e., 4 4.096V) from the last sampled voltage (as stored on C HOLD ). If the A/D clock source is selected as RC, a time added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2003 Microchip Technology Inc. ...
Page 105
... Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 7.1 for minimum conditions. 2003 Microchip Technology Inc. ( 131 ...
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... PIC12F629/675 NOTES: DS41190C-page 104 2003 Microchip Technology Inc. ...
Page 107
... FIGURE 13-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5 2003 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline ...
Page 108
... DS41190C-page 106 vs. V OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD 125 5.0 5.5 - 5.5 2003 Microchip Technology Inc. ...
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... FIGURE 13-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 2003 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline ...
Page 110
... DS41190C-page 108 WITH BOD ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical BOD 4.5 V (V) DD WITH CMP ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical Comparator I PD 3.0 3.5 4.0 4.5 V ( 125 5 5.5 - 125 5.0 5.5 2003 Microchip Technology Inc. ...
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... FIGURE 13-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 2003 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A/D I ...
Page 112
... DS41190C-page 110 WITH A/D ENABLED vs. V OVER TEMP (+125°C) DD Typical A 3.5 4 4.5 V (V) DD WITH T1 OSC ENABLED vs Typical 3.0 3.5 4.0 4.5 V (V) DD 125 5 5.5 OVER TEMP (-40°C TO +125°C), - 125 5.0 5.5 2003 Microchip Technology Inc. ...
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... FIGURE 13-14: TYPICAL 2.5 2003 Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT ...
Page 114
... DS41190C-page 112 = 3.5V) DD Internal Oscillator Frequency vs Temperature 0°C 25°C 85°C Temperature (°C) Internal Oscillator Frequency 3.0V 3.5V 4.0V 4.5V V (V) DD -3sigma average +3sigma 125°C WITH 0.1µF AND 0.01µF DD -3sigma average +3sigma 5.0V 5.5V 2003 Microchip Technology Inc. ...
Page 115
... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5 2003 Microchip Technology Inc. (-40°C TO +125°C) DD WDT Time-out 3 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 DS41190C-page 113 ...
Page 116
... PIC12F629/675 NOTES: DS41190C-page 114 2003 Microchip Technology Inc. ...
Page 117
... Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2003 Microchip Technology Inc. PIC12F629/675 Example 12F629-I ...
Page 118
... L p MILLIMETERS MIN NOM MAX 8 2.54 3.56 3.94 4.32 2.92 3.30 3.68 0.38 7.62 7.94 8.26 6.10 6.35 6.60 9.14 9.46 9.78 3.18 3.30 3.43 0.20 0.29 0.38 1.14 1.46 1.78 0.36 0.46 0.56 7.87 9.40 10. 2003 Microchip Technology Inc. ...
Page 119
... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2003 Microchip Technology Inc. PIC12F629/675 φ ...
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... MILLIMETERS* MIN NOM MAX 8 1.27 BSC 0.85 1.00 0.65 0.80 0.00 0.01 0.05 0.20 REF. 4.92 BSC 4.67 BSC 3.85 4.00 4.15 5.99 BSC 5.74 BSC 2.16 2.31 2.46 0.35 0.40 0.47 0.50 0.60 0.75 .356 12 2003 Microchip Technology Inc. ...
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... Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) Land Pattern and Solder Mask SOLDER MASK p PACKAGE EDGE Dimension Limits Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter Drawing No. C04-2113 2003 Microchip Technology Inc. Units INCHES MIN NOM MAX p .050 BSC B .014 .016 .019 L .020 ...
Page 122
... PIC12F629/675 NOTES: DS41190C-page 120 2003 Microchip Technology Inc. ...
Page 123
... Added notes to indicate Microchip programmers maintain all calibration bits to factory settings and the PIC12F675 ANSEL register must be initialized to configure pins as digital I/O. Updated MLF-S package name to DFN-S. 2003 Microchip Technology Inc. PIC12F629/675 APPENDIX B: DEVICE DIFFERENCES The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1 ...
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... These differences may cause this device to perform differently in your application than the earlier version of this device. 2003 Microchip Technology Inc. ® PIC12F6XX 20 MHz 1024 bytes 10-bit 64 bytes ...
Page 125
... Saving STATUS and W Registers in RAM ................. 64 Write Verify ................................................................. 49 Code Protection .................................................................. 67 Comparator ......................................................................... 35 Associated Registers .................................................. 40 Configuration............................................................... 37 Effects of a RESET ..................................................... 39 I/O Operating Modes................................................... 37 Interrupts..................................................................... 40 2003 Microchip Technology Inc. Operation.................................................................... 36 Operation During SLEEP............................................ 39 Output......................................................................... 38 Reference ................................................................... 39 Response Time .......................................................... 39 Comparator Specifications................................................ 100 Comparator Voltage Reference Specifications................. 100 Configuration Bits ............................................................... 52 Configuring the Voltage Reference ...
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... Special Features of the CPU .............................................. 51 Special Function Registers ................................................... 8 Special Functions Registers Summary................................. 9 T Time-out Sequence ............................................................ 57 Timer0................................................................................. 27 Associated Registers .................................................. 29 External Clock............................................................. 28 Interrupt ...................................................................... 27 Operation .................................................................... 27 T0CKI ......................................................................... 28 Timer1 Associated Registers .................................................. 33 Asynchronous Counter Mode ..................................... 33 Reading and Writing ........................................... 33 Interrupt ...................................................................... 31 Modes of Operations .................................................. 31 Operation During SLEEP............................................ 33 Oscillator..................................................................... 33 2003 Microchip Technology Inc. ...
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... Case 1 ................................................................ 60 Case 2 ................................................................ 60 Time-out Sequence on Power-up (MCLR Tied ).................................................... 60 Timer0 and Timer1 External Clock ............................. 99 Timer1 Incrementing Edge.......................................... 31 Timing Parameter Symbology............................................. 93 V Voltage Reference Accuracy/Error ..................................... 39 W Watchdog Timer Summary of Registers ................................................ 65 Watchdog Timer (WDT) ...................................................... 64 WWW, On-Line Support ....................................................... 3 2003 Microchip Technology Inc. DS41190C-page 125 ...
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... NOTES: DS41190C-page 126 2003 Microchip Technology Inc. ...
Page 129
... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2003 Microchip Technology Inc. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...
Page 130
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41190C-page 128 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41190C 2003 Microchip Technology Inc. ...
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... The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. XXX Examples: Pattern ...
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... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No ...