20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet - Page 183

• Manufacturer Part Number: 20-668-0024
• Description: IC CPU RABBIT4000 128-LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0024

• Processor Type: Rabbit 4000 8-bit
• Speed: 60MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 20-668-0022; 316-1078

19. DMA C
HANNELS
19.1 Overview
There are eight independent DMA channels on the Rabbit 4000. All eight channels are
identical, and are capable of transferring data to or from memory, external I/O, or internal
I/O. The priority between the channels can be either fixed or rotating, and the DMA use of
the bus can be limited to guarantee interrupt latency or CPU throughput. The DMA channels
are capable of special handling for the last byte of data when sending data to selected
internal I/O addresses (such as the HDLC serial ports or to the Ethernet peripheral), and
can also transfer end-of-frame status after transferring data from selected internal I/O
addresses.
The DMA channels can watch the data being transferred and can terminate a transfer
when a particular byte is matched. A mask is available for the byte match to allow termi-
nation only on particular bit settings in the data instead of an exact byte match.
Memory-to-memory transfers proceed at the maximum transfer rate unless they are gated
by an external request signal or the internal timed request. Transfers to or from a number
of internal I/O addresses are controlled by transfer request signals. These transfer request
signals are connected automatically as a function of the internal I/O address loaded into
the DMA channel. Note that if both the source and the destination are internal I/O, the
source transfer request is used by the DMA channel.
The DMA channels are inherently byte-oriented, so while DMA transfers can be done
from a 16-bit memory, DMA transfers to a 16-bit memory can only be done if the 16-bit
memory is set up to allow byte writes. See Chapter 5 for more information.
There are two inputs available for requests linked to external I/O devices. These two exter-
nal requests may be assigned to any DMA channel. These requests may also be used by a
channel that has an internal I/O as a destination. In this case, the external request acts as a
“flow control” signal for the DMA transfers because the external request is “ANDed” with
the automatically connected internal request.
To facilitate periodic DMA transfers, there is also an internal timed request. This request is
generated from a programmable 16-bit counter and may be assigned to any DMA channel.
As in the case of the external requests, this request is “ANDed” with any internal or exter-
nal request that is also assigned to that DMA channel. This periodic request can be pro-
grammed to transfer one byte or an entire buffer. The single-byte option is useful for
driving an output port to create a sampled waveform, while the entire-buffer option can be
used, for example, to send precisely timed serial messages over a serial port.
Chapter 19 DMA Channels
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