Z8018008VSG Zilog, Z8018008VSG Datasheet - Page 20

IC 8MHZ Z180 CMOS ENH MPU 68PLCC

Z8018008VSG

Manufacturer Part Number
Z8018008VSG
Description
IC 8MHZ Z180 CMOS ENH MPU 68PLCC
Manufacturer
Zilog
Datasheet

Specifications of Z8018008VSG

Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3886
Z8018008VSG

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PS014004-1106
Timer Reload
Timer Data
TDE Flag
TIF Flag
T
Register
Register
OUT
Note:
RESET
Clocked Serial I/O (CSIO). The
receiver. This channel can be used for simple high-speed data connection to another micro-
processor or microcomputer.
system design must ensure that the constraints of half-duplex operation are met. Transmit
and Receive operations cannot occur simultaneously. For example, if a
attempted while the
f
Figure 5. Timer Initialization, Count Down, and Reload Timing
FFFFh
TRDR
transmit data is still being shifted out causes the shift data to be immediately
Timer Data Register
WRITE (0004h)
FFFFh
Timer Reload Register WRITE (0003h)
Timer Data
Reg. = 0001h
is not buffered. Attempting to perform a
0004h
0003h
CSIO
Figure 6. Timer Data Register
0003h
WRITE
0 < t < 20 f
20 f
is receiving data, a
a 1
0002h
TRDR
20 f
Timer Data
Reg. = 0000h
to TDE
CSIO
0001h
20 f
is used for both
channel provides a half-duplex serial transmitter and
0000h
20 f
CSIO
0003h
20 f
Reload
does not work.
0002h
CSIO
20 f
0001h
transmission and reception. The
CSIO
20 f
Timer Data Register READ
Timer Control Requestor READ
0000h
20 f
transmit while the previous
Microprocessor Unit
0003h
20 f
CSIO
Reload
transmission is
Architecture
Z80180
14

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