Z8S18010FSG Zilog, Z8S18010FSG Datasheet - Page 67
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Z8S18010FSG
Manufacturer Part Number
Z8S18010FSG
Description
IC 10MHZ STATIC Z180 80-QFP
Manufacturer
Zilog
Datasheet
1.Z8S18010PSG.pdf
(71 pages)
Specifications of Z8S18010FSG
Processor Type
Z180
Features
Enhanced Z180
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-BQFP
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4296
Z8S18010FSG
Z8S18010FSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18010FSG
Manufacturer:
Zilog
Quantity:
426
ZiLOG
dress (on 4-KB boundaries) for Common Area 1. This con-
dition also determines the most recent address of the Bank
Area. All bits of
The Z8S180/Z8L180 is descended from two different an-
cestor processors, ZiLOG’s original Z80 and the Hitachi
64180. The Operating Mode Control Register (
be programmed to select between certain differences be-
tween the Z80 and the 64180.
A
0
–A
18
MREQ
D
0
(A
–D
RD
M1
ST
19
7
)
are set to
T
1
T
2
PC
specifies the start (Low) ad-
1
EDH
T
during
3
T
1
T
2
.
4DH
T
3
) can
PC+1
T
I
T
(on 4-KB boundaries) for the Bank Area. This condition
also determines the most recent address of Common Area
0
set to a
When
opcode fetch cycle, the
first machine cycle of the
On the Z8S180/Z8L180, this choice makes the processor
fetch one
wait-state memory, the processor uses three clock machine
cycles that are not fully Z80-timing-compatible.
When
ing instruction fetch cycles. After fetching one
tion with normal timing, the processor returns and refetches
the instruction using Z80-compatible cycles that drive
Low. This timing compatibility may be required by external
Z80 peripherals to properly decode the
I
. All bits of
T
I
1
T
1
during reset.
instruction. When fetching a
0
1
T
, the processor does not drive
, the
2
are set to
T
EDH
This bit controls the
3
PC
output is asserted Low during the
T
specifies the start (Low) address
1
I
acknowledge cycle, and the
during
acknowledge.
T
1
T
2
PC+1
4DH
T
3
.
output and is
instruction.
from zero-
T
Low dur-
I
instruc-