Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 6

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

PS014004-1106
DMA Source Address Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DMA Destination Address Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Byte Count Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DMA Source Address Register, Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . 54
DMA Source Address Register, Channel 0H . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Source Address Register Channel 0B . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Destination Address Register Channel 0L . . . . . . . . . . . . . . . . . . . . . 56
DMA Destination Address Register Channel 0H . . . . . . . . . . . . . . . . . . . . . 56
DMA Destination Address Register Channel 0B . . . . . . . . . . . . . . . . . . . . . 56
DMA Byte Count Register Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Byte Count Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Byte Count Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DMA Memory Address Register, Channel 1L . . . . . . . . . . . . . . . . . . . . . . . 59
DMA Memory Address Register, Channel 1H . . . . . . . . . . . . . . . . . . . . . . . 60
DMA Memory Address Register, Channel 1B . . . . . . . . . . . . . . . . . . . . . . . 60
DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Microprocessor Unit
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