XS1-L02A-QF124-C5-THS XMOS, XS1-L02A-QF124-C5-THS Datasheet
XS1-L02A-QF124-C5-THS
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XS1-L02A-QF124-C5-THS Summary of contents
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... XS1-L2 124QFN Datasheet Publication Date: 2010/06/16 Copyright © 2010 XMOS Ltd. All Rights Reserved. Version 1.5 ...
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... XS1-L2 124QFN Datasheet (1.5) 1 Description The XS1- member of the XS1-L family of XMOS devices. The XS1-L family blends a power- ful programmable fabric based on multi-threaded processors with a high-level programming language design flow. XMOS chips are general-purpose pro- grammable devices that can be used in a wide range of applications and systems. The XS1-L2 device is based on the XMOS XCore™ ...
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... XS1-L2 124QFN Datasheet (1.5) 2 Signal Descriptions This section describes the external signal pins of the XS1-L2 in the 124 QFN package. The following I/O type conventions are used in this document 2.1 XCore Signals The XS1-L2 124QFN device provides 84 XCore signals that can be used for generic I/O ports or XMOS Links ...
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... XS1-L2 124QFN Datasheet (1.5) 2.1.3 Precedence Ports and XMOS Links are connected to pins on the XS1-L2 by the program running on the device. The ports and links are multiplexed and follow a defined precedence if they overlap on the same core XMOS Link is enabled, the link has access to the pins; the pins of the underlying ports are disabled ...
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... XS1-L2 124QFN Datasheet (1.5) 2.2 Port Pin Table Signal Pin ID XMOS LINKS Core 0 Core 1 5bit XnD0 A15 A39 XnD1 A16 A40 XLA4out XnD2 A5 A41 XLA3out XnD3 A6 A42 XLA2out XnD4 A7 A43 XLA1out XnD5 A8 A44 XLA0out XnD6 A9 A45 XLA0in XnD7 A10 A46 XLA1in ...
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... XS1-L2 124QFN Datasheet (1.5) 2.3 System Service Pin Table Pin ID Signal B7 CLK B37 DEBUG B33 MODE0 B34 MODE1 B35 MODE2 B36 MODE3 A35 MODE4 B32 OTP_VDDIO 2.4 Core Power and Ground Pin Table Pin ID Signal A19 VDD A34 VDD A53 VDD ...
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... XS1-L2 124QFN Datasheet (1.5) 2.7 XMOS Link Pin Table See Section 2.2 Port Pin Table www.xmos.com 7/28 ...
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... XS1-L2 124QFN Datasheet (1.5) 3 System Services System Services are required to support correct device behavior. These signals control clocking, reset and boot behavior of the device. 3.1 Clock control signals These signals control the PLL of the XS1-L2 Signal Pin ID PLL_AVDD A38 PLL_AGND A37 ...
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... XCores boot up according to the boot mode (see MODE). 3.3 SPI Interface To boot the master core on the XS1-L2 device from an SPI interface, the SPI device must be connected as follows: Boot Mode None - Both cores wait to be booted (via JTAG) ...
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... MODE[4]=1. 3.4 Power Control Unit The XS1-L2 power control unit (PCU) provides control signals to isolate the core voltage of the device and reapply it under a controlled condition known as sleep mode. The device recovers into functional mode under the control of an external PCU_WAKE signal or an internal timer ...
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... OTP_VDDIO OTP Power Supply. Must be 3V3. This supply must be at its nominal level before the core supply is enabled. 3.6 JTAG Operation The XS1-L2 device contains a standard 5 pin JTAG interface, which allows the following functionality: Boundary scan testing for verifying printed circuit board connectivity. ...
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... XS1-L2 124QFN Datasheet (1.5) XCore, Switch and OTP for such actions as loading code and debugging. Both TAPs have an instruction register length of 4. From reset, the chip TAP is in BYPASS so simply presents an extra 1-bit into the scan chain when shifting data. If access to the XCore/Switch/OTP is required, the ChipTAP sets internal multiplexers which optionally add in additional TAPs into the JTAG chain for each of the Switch, XCore and OTP ...
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... XS1-L2 124QFN Datasheet (1.5) The OTP User ID is read from the OTP and can be programmed as a means of identifying versions of OTP programmed devices. Unprogrammed devices have these bits set to zero. www.xmos.com 13/28 ...
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... XS1-L2 124QFN Datasheet (1. and Switching Characteristics 4.1 Operating Conditions Symbol Parameter VDD(IO) I/O DC supply voltage VDD(CORE) Core DC supply voltage AVDD(PLL) PLL analogue supply Cl XCore I/O load capacitance Operating temperature range (Commercial) Ta Operating temperature range (Industrial) Tj Junction temperature Tstg Storage temperature 4.2 DC Characteristics ...
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... KV MM 200 V 4.4 Reset Timing XS1 devices include an internal counter which ensures the PLL has had time to lock before the rest of the device is brought out of reset. An active low pulse on RST_N clears this counter. Counting begins when RST_N is de-asserted. Parameters Reset pulse width ...
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... For a more detailed analysis see 4.6 Clock XS1-L devices use an input clock frequency, supplied by the user on the CLK pin, to drive the PLL and obtain the system clock. The nominal frequency of the clock for all XS1 family components is 20MHz but other clock frequencies can be used ...
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... Memory 4.7.1 Internal static memory The XS1-L2 has a total of 128KBytes (64KBytes per core) of fast internal static memory for high rates of data throughput. Each internal memory access consumes one core clock cycle. There is no dedicated external memory interface, although memory can be expanded through appropriate use of the ports ...
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... ClkBlk The Input Valid window parameter relates to the capability of the XS1-L family devices to capture data input to the chip with respect to an external clock source. This parameter can be calculated as the sum of the input setup time and input hold time with regard to the external clock as measured at the L2 device pins. The output invalid window specifi ...
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... XS1-L2 124QFN Datasheet (1.5) 4.10 JTAG Timing All JTAG operations are synchronous to TCK apart from the global asynchronous reset TRST_N. Parameters TCK frequency (debug) TCK frequency (boundary scan) T SETUP T HOLD T CLOCK to OUT Notes: 1. Timing applies to TMS and TDI inputs 2. Timing applies to TDO output from negative edge of TCK ...
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... XS1-L2 124QFN Datasheet (1.5) 5 Package Details 5.1 Package Pin Layout The following diagram shows the pin name and location for the 124 QFN package (top view A10 B8 A11 B9 A12 B10 A13 B11 A14 B12 A15 B13 A16 B14 A17 A18 PAD www ...
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... XS1-L2 124QFN Datasheet (1.5) 5.2 Package Signal Layout The following diagram shows the signal name and location for the 124 QFN package (top view). GND VDDIO X0D35 VDDIO X0D34 PCU_WAKE X0D2 PCU_GATE X0D3 PCU_VDDIO X0D4 PCU_VDD X0D5 PCU_CLK X0D6 CLK X0D7 ...
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... XS1-L2 124QFN Datasheet (1.5) 5.3 Package Mechanical Details www.xmos.com 22/28 ...
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... XS1-L2 124QFN Datasheet (1.5) 5.4 Package Marking Details USMMYYL2 I4 LLLLLL.LL Manufacture Date Code USMMYYL2 USMMYYL2 C5 USMMYYL2 I4 USMMYYL2 I5 Manufacturing Date Code Qualification/Speed(Optional) Lot Code Part Number XS1-L02A-QF124-C4 XS1-L02A-QF124-C5 XS1-L02A-QF124-I4 XS1-L02A-QF124-I5 www.xmos.com 23/28 ...
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... XS1-L2 124QFN Datasheet (1.5) 6 Ordering information Part numbering and ordering information. XMOS Ident & Architecture Number of XCores Revision Mask (A-Z) Package Type Pin Count Temp Grade (C commercial 0-70C) Speed Grade (4 normal speed) 6.1 Orderable part numbers Part Number Speed XS1-L02A-QF124-C4 800MIPS ...
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... Device Configuration Example schematic diagrams detailing minimal system configurations may be found at: http://xmos.com/support/silicon 8 Addendum 8.1 USB ULPI Mode When using the XS1-L2 with ULPI, the ULPI signals must only be connected to the following pins on one core: Pin Name Core 0 XnD12 A55 ...
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... XS1-L System Specification XMOS Tools User Guide XS1 Assembly Language Manual XMOS XS1 32-Bit Application Binary Interface XS1-L Clock Frequency Control Application Note XS1 Port I/O Timing Application Note XS1-L Link Performance and Design Guidelines Estimating Power Consumption For XS1-L Devices ...
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... XS1-L2 124QFN Datasheet (1.5) 10 Document History Date Release 2009-12-18 1v0 2010-01-07 1v1 2010-01-19 1.2 2010-03-15 1.3 2010-05-20 1.4 2010-06-16 1.5 Comment First release Section 3.2, NOTE updated "... the boot mode indicated on the MODE[3:2] pins is ignored." Added Package marking section. ...
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... XS1-L2 124QFN Datasheet (1.5) 11 Errata To guarantee a logic low is seen on the following pins, the driving circuit should present an impedance of less than 100 ohms to ground. Pin ID A35 B8 B37 B36, B35, B34, B33 B13 B11 B10 B12 B55 Usually this is not a problem for CMOS drivers driving single inputs, however, if one or more of these inputs are placed in parallel, additional logic buff ...