GCIXP1240AB Intel, GCIXP1240AB Datasheet - Page 13
GCIXP1240AB
Manufacturer Part Number
GCIXP1240AB
Description
IC MPU NETWORK 200MHZ 432-BGA
Manufacturer
Intel
Specifications of GCIXP1240AB
Rohs Status
RoHS non-compliant
Processor Type
Network
Features
32-bit StrongARM RISC Core
Speed
200MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
432-BGA
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Other names
837151
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Datasheet
Table 1. 64-bit IX Bus Receive Remainder Cycles, No Status Transfer
Table 2. 64-bit IX Bus Receive Remainder Cycles, with Status Transfer
Table 3. 32-bit IX Bus Receive Remainder Cycles, No Status Transfer
Table 4. 32-bit IX Bus Receive Remainder Cycles, with Status Transfer
In addition, a shared IX Bus mode is supported in 64-bit bidirectional mode. Refer to the list at the
bottom of
tri-state.
The IX Bus and Intel devices using the IX Bus, such as the 21440 and IXF1002, observe a
pipelined bus protocol. When receive transfers are terminated early, the pipeline continues to cause
several extra bus cycles depending on when the EOP signal was asserted. Data is a “don't care” for
these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a
possible status transfer if the device were programmed to support it. Slave devices must drive valid
logic levels on the FDAT data pins during these cycles.
The tables below show the number of total IX Bus data cycles that will occur for a burst with EOP
asserted at specific clocks for 64-bit and 32-bit IX Bus modes. In each case, the tables show IX Bus
cycles with and without the optional status transfer cycle. Refer to the IX Bus Protocol Timing
diagrams
# of bus cycles in burst:
# of Don’t Care cycles:
# of bus cycles in burst:
Status transfer
# of Don’t Care cycles:
NOTE:
# of bus cycles in burst:
# of Don’t Care cycles:
# of bus cycles in burst:
1. Status transfer occurs on a subsequent IX Bus status cycle.
EOP signaled on this
EOP signaled on this
EOP signaled on this
EOP signaled on this
(Figure 21
Table 26
cycle:
cycle:
cycle:
cycle:
for the signals that the IX Bus masters must drive and IX Bus slaves must
through
1
5
1
5
4
Figure
1
5
4
1
5
1
3
2
6
2
6
4
54) when interpreting these tables.
3
7
3
7
4
2
6
4
2
6
1
3
4
8
4
8
4
5
9
5
9
4
3
7
4
3
7
1
3
10
10
6
6
4
11
11
7
7
4
4
8
4
4
8
1
3
Intel
12
12
8
8
4
®
13
13
9
9
4
IXP1240 Network Processor
5
8
3
5
8
1
2
10
14
10
14
4
11
15
15
11
4
6
8
2
6
8
1
1
12
16
12
16
4
13
16
13
16
3
7
8
1
7
8
1
0
14
16
14
16
2
15
16
15
16
Note 1
1
8
8
0
8
8
0
16
16
16
16
13
0
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