Z8L18020VSC Zilog, Z8L18020VSC Datasheet - Page 46

• Manufacturer Part Number: Z8L18020VSC
• Description: IC 20MHZ LOW PWR S180 68-PLCC
• Manufacturer: Zilog

Specifications of Z8L18020VSC

• Processor Type: Z80
• Features: Enhanced DMA Support
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

a CPU interrupt request is generated. Program access of
Register addresses
for channel 0 and channel 1, respectively.
The CSI/O Control/Status Register (
itor CSI/O status, enable and disable the CSI/O, enable and
completion of an 8-bit data transmit or receive operation.
If End Interrupt Enable (
and
erate a CPU interrupt request. The interrupt request is in-
hibited if
started by setting
is enabled. In internal clock mode, the data clock is output
from the
on the
only occurs if
is read or written.
pin. In either case, data is shifted in on the
mode.
is reset to
pin. In external clock mode, the clock is input
08H
to
1
0
and
. When
.
is set to
1
. The CSI/O clears
09H
) bit =
is cleared to
A CSI/O receive operation is
is cleared to
hold the ASCI receive data
1
is set to
by the CSI/O to indicate
1
when
is set to
0
0
) is used to mon-
1
during
, the data clock
during
is set to
1
to
0
to gen-
when
1
,
.
disable interrupt generation, and select the data clock speed
and source.
pin in synchronization with the (internal or external) data
clock. After receiving 8 bits of data, the CSI/O automati-
cally clears
by
1
is started by setting
clock is enabled. When in internal clock mode, the data
clock is output from the
the clock is input on the
ed out on the
ternal) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears
quests an interrupt if enabled by
at the same time.
mode.
) is generated.
to
0
pin synchronous with the (internal or ex-
,
is set to
to
is cleared to
1
. When
pin. In either case, data is shift-
1
and
A CSI/O transmit operation
pin. In external clock mode,
, and an interrupt (if enabled
to
0
, sets
0
are never both set to
is set to
during
1
.
to
and
1
1
, the data
, and re-
ZiLOG
and
are