Z8S18010FEG Zilog, Z8S18010FEG Datasheet - Page 60

• Manufacturer Part Number: Z8S18010FEG
• Description: IC 10MHZ STATIC Z180 80-QFP
• Manufacturer: Zilog

Specifications of Z8S18010FEG

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
Table 16 indicates all DMA transfer mode combinations of
fers are not implemented, 12 combinations are available.
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, two automatic transfer timing modes are se-
lectable: burst (
,
* Includes memory mapped I/O.
,
, and
. Because I/O to/from I/O trans-
) and cycle steal (
When chan-
).
completes (as indicated by the byte count register = ). In
cycle steal mode, the CPU is provided a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer ignoring
is cleared to
0
during
.
ZiLOG
.