Z84C9008VEC Zilog, Z84C9008VEC Datasheet - Page 23

• Manufacturer Part Number: Z84C9008VEC
• Description: IC 8MHZ Z80 KIO XTEMP 84-PLCC
• Manufacturer: Zilog

Specifications of Z84C9008VEC

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5. AC Characteristics of the Z84C90 (Continued)
Table 6.Daisy Chain Parameters
PS011802-0902
No. Symbol
63 TrRxC
64 TfRxC
65 TsRxD(RxCr)
66 ThRxCr(RxD)
Notes:
No. Symbol
18
67 TdRxCr(W/Rf) RxC Rise to W/RDY Fall Delay
68 TdRxCf(INTf)
69 TdRxCr
70 TsSYNCf
71 TdCf(IEOr)
72 TdCf(IEOf)
73 ThDI(M1r,Rdr) Data Hold Time to M1 Rise or RD
74 TsM1/RD(C)
1. Maximum SIO data rate is f(CLOCK) divided by 5.
2. For a Z80 CPU above 8 MHz, one Wait state is required to meet this parameter.
3. These daisy chain parameters include contributions from the PIO, SIO, and CTC cells, and vary slightly
4. Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
5. units are TcC.
1
depending on how these are ordered by the KIO command register. See Table 5.
(SYNCf)
(RxCr)
TdM1(IEO)
Parameter
RxC Rise Time
RxC Fall Time
RxD to RxC Rise Setup
RxC Rise to RxD Hold Time
(Ready Mode)
RxC to INT Fall Delay
RxC Rise to SYNC Fall Delay
(Output Mode)
SYNC Fall to RxC Rise Setup
(External Sync Mode)
Clock Fall to IEO Rise Delay
Clock Fall to IEO Fall Delay
Rise
Setup time for M1 and RD to clock
Rising (with Data Valid)
Parameter
(PIO at #1)
(CTC at #1)
(SIO at #1)
5
5
8 MHz
Min
Min
-100
8MHz
80
10
10
20
0
4
0
Max
160
180
230
KIO Serial/Parallel Counter Timer
Max
110
60
60
13
13
90
7
10 MHz
Min
-100
Min
60
10
10
20
0
4
0
10MHz
Max
150
150
200
Max
60
60
13
13
75
90
1
7
12 MHz
Min
Min Max U/M
12MHz
Max U/M
125 ns
125 ns
200 ns
Z84C90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18