EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 58
EZ80190AZ050SC00TR
Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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PS006614-1208
Table 13. Port x Data Registers (PA_DR = 96h, PB_DR = 9Ah, PC_DR = 9Eh, PD_DR = A2h)
Port
Table 14. Port x Data Direction Registers (PA_DDR = 97h, PB_DDR = 9Bh, PC_DDR = 9Fh,
Port
Table 15. Port x Alternate Registers 1
Port
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Reset
CPU Access
Note: R/W = Read/Write.
x
x
x
In conjunction with the other GPIO Control Registers, the Port x Data Direction registers,
listed in
tion see
In conjunction with the other GPIO Control Registers, the Port x Alternate Register 1,
listed in
tion see
In conjunction with the other GPIO Control Registers, the Port x Alternate Register 2,
listed in
information see
Data Direction Registers
Alternate Registers 1
Alternate Registers 2
Table 12
Table 12
Table 16
Table
Table
14, control the operating modes of the GPIO port pins. For more informa-
15, control the operating modes of the GPIO port pins. For more informa-
Table 12
on page 43.
on page 43.
on page 49, control the operating modes of the GPIO port pins. For more
R/W
R/W
R/W
X
7
7
1
7
0
on page 43.
R/W
R/W
R/W
X
6
6
1
6
0
PD_ALT1 = A4h)
PD_DDR = A3h)
(PA_ALT1 = 98h, PB_ALT1 = 9Ch, PC_ALT1 = A0h,
R/W
R/W
R/W
X
5
5
1
5
0
R/W
R/W
R/W
X
4
4
1
4
0
R/W
R/W
R/W
X
3
3
1
3
0
R/W
R/W
R/W
X
2
2
1
2
0
General-Purpose Input/Output
Product Specification
R/W
R/W
R/W
X
1
1
1
1
0
R/W
R/W
R/W
X
0
0
1
0
0
eZ80190
48
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