EZ80190AZ050EC00TR Zilog, EZ80190AZ050EC00TR Datasheet - Page 78
![IC EZ80 ACCLAIM 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050EC00TR
Manufacturer Part Number
EZ80190AZ050EC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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UART Functional Description
UART Functions
PS006614-1208
UART Transmitter
The core uses an externally-provided clock from the Baud Rate Generator for the serial
transmit/receive function. The UART module supports all of the various options in the
asynchronous transmission and reception protocol including:
•
•
•
•
•
The UART contains 16-byte FIFOs in each direction. The FIFOs can be enabled or dis-
abled by the application. The receive FIFO features trigger-level detection logic, which
enables the processor to block transfer data bytes from the receive FIFO.
The UART data transfer rate is calculated in the following equation:
The UART function implements:
•
•
•
The transmitter block controls the data transmitted on the TXD output. It implements the
FIFO, accessed through the UARTx_THR register, the transmit shift register, the parity
generator, and control logic for the transmitter to control parameters for the asynchronous
communications protocol.
The UARTx_THR is a Write Only register. The processor writes the data byte to be trans-
mitted into this register. In FIFO mode, up to 16 data bytes can be written through the
UARTx_THR register. The data byte from the FIFO is transferred to the transmit shift reg-
ister and transmitted on the TXD pin. After SYNC_RESET, the UARTx_THR register is
empty so the Transmit Holding Register Empty (THRE) bit (bit 5 of the UARTx_LSR reg-
UART Data Transfer Rate (bits/s) =
5 to 8-bit transmit/receive
Start bit generation and detection
Parity generation and detection
Stop bit generation and detection
Break generation and detection
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
16 x Baud Rate Generator Divisor
System Clock Frequency
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80190
68
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