Z8019533FSG Zilog, Z8019533FSG Datasheet
Z8019533FSG
Specifications of Z8019533FSG
Available stocks
Related parts for Z8019533FSG
Z8019533FSG Summary of contents
Page 1
...
Page 2
... Document Disclaimer © 2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ...
Page 3
Preface DOCUMENT ASSUMPTIONS AND CONVENTIONS The following assumptions and conventions have been adopted to provide clarity and ease of use: • Use of the Words Set and Clear The words set and clear imply that a register bit or a ...
Page 4
Z80185/Z80195 User Manual ii Hexadecimal values are designated by an upper-case letter H as well as the use of Courier font. For example: • Use of All Upper-Case Letters The use of all upper-case letters designates the names of states ...
Page 5
... TRADEMARKS Several trademarks appear in this product specification. The following items are trademarks of ZiLOG, Inc.: • Z80 • Z180 • ESCC • SCC • Z80185 • Z80195 Z80185/Z80195 User Manual iii UM001001-1000 ...
Page 6
Z80185/Z80195 User Manual iv UM001001-1000 ...
Page 7
...
Page 8
...
Page 9
...
Page 10
...
Page 11
(TRDR:0BH) (CNTR:0AH) ...
Page 12
I/O Address = CH0, OEH, OFH, CH1: 16H, 17H) (waiting for mnemonic) (%DE) ...
Page 13
PARC: DA ...
Page 14
...
Page 15
...
Page 16
...
Page 17
...
Page 18
...
Page 19
...
Page 20
...
Page 21
...
Page 22
...
Page 23
...
Page 24
...
Page 25
• • • Œ • • • Š Œ Œ ...
Page 26
• • • Œ • Œ ...
Page 27
ROMCS RAMCS ...
Page 28
* * * & & & ...
Page 29
...
Page 30
...
Page 31
0066H ...
Page 32
OUT OUT ...
Page 33
CTS. RTS ...
Page 34
Π...
Page 35
RESET 1 ...
Page 36
XX40 NN3F NN 1 00F8 FFFF XXD7 XXF8 XXFF 0040 0 NN00 00D7 ...
Page 37
à • • • • • • • ...
Page 38
• • • • • ...
Page 39
...
Page 40
...
Page 41
CCR OMCR ...
Page 42
PC 1 ...
Page 43
...
Page 44
W 3 ...
Page 45
WAIT ...
Page 46
WAIT MREQ ...
Page 47
...
Page 48
00000H ...
Page 49
...
Page 50
IN0 OUT0 0 ...
Page 51
ICR • • • xxD8-xxF1 • IORQ W MREQ ...
Page 52
...
Page 53
...
Page 54
...
Page 55
...
Page 56
...
Page 57
...
Page 58
...
Page 59
...
Page 60
...
Page 61
...
Page 62
QG ...
Page 63
UG ...
Page 64
...
Page 65
...
Page 66
...
Page 67
...
Page 68
...
Page 69
...
Page 70
OMCR ancestor ...
Page 71
MITE IOC MIE MIE OMCR 3EH RETI RETI MI RETI 0 RETI RETI ...
Page 72
MITE IOC MIE MIE MIE 1 ...
Page 73
ICR 1 ...
Page 74
ICR: 3FH IOA7 IOA6 (IOSTP ...
Page 75
CCR: 1FH ...
Page 76
ICR5 SLP (ICR5 Bit 6 0 Bit 3 ICR5 Bit 6 1 Bit 3 ICR5 & ...
Page 77
RTSO BUSACK MREQ IORQ RFSH HALT ...
Page 78
CCR IER DF ROMCS RAMCS IOCS RTS DTR TRXC 1 ...
Page 79
ROMCS ROMCS ROMCS ROMCS EDH ROMCS ...
Page 80
RTS0 CTS0 RTS0 CTS0 f/ f ...
Page 81
ROMBR 03 ...
Page 82
ROMBR ROMBR: ECH ROMBR ROMBR WAIT 08000H ROMBR 03H ROMBR 0 ROMBR ...
Page 83
RAMUBR: EAH RAMUBR RAMLBR: EBH RAMCS RAMLBR RAMUBR ROMBR ...
Page 84
ICR 0040..00D7 00F8..01D7, 01F8..02D7, ..., FEF8..FFD7, FFF8..FFFF 0000..003F, 0080..00D7, 00F8.. 01D7, 01F8..02D7, ... , FEF8..FF07, FFF8..FFFF 0000..007F, 00C0..00D7, 00F8..01D7, 01F8..02D7, ..., FEF8..FFD7, FFF8..FFFF. 0040..00D7, 00F8..FFFF 0000..003F, 0080..00D7, 00F8..FFFF 0000..007F, 00C0..00D7, 00F8..FFFF WAIT WAIT WAIT f ...
Page 85
MI IWI1..IWI0 DCTRL DCTRL INT0 ...
Page 86
DCTRL 11 WSGCS MI RD MWI1..MWI0 00 ...
Page 87
RAMCS ROMCS RAMCS ROMCS WSGCS: D8 ...
Page 88
1 ...
Page 89
Halt Halt Halt ...
Page 90
CCR3 SLP INT1 INT2 IEF 1 DI ICR5 CCR6 0 f SLP SLP IEF 0 EI ...
Page 91
ICR 1 ICR SLP ICR5 1 CCR6) SLP CCR5 1 0 ICR CCR3 ...
Page 92
NMI ICR SLP 1 CCR 1 EI SLP CCR 1 1, CCR) 1 SLP IEF1 ...
Page 93
Divide-By-Two CCR Bit 7 0 CCR Bit Divide-By-Two SLP 01 1 SLP Bit 3 Bit SLP 0 ...
Page 94
SLP IEF1 SLP CCR 1 CCR INT2 CCR ...
Page 95
...
Page 96
ITC: 34H TRAP 1 PC PC-2 ...
Page 97
INT2 INT1 ITE0 INT0 1 0000H RST 0 ITC 00000H 1 ITE1 ITE2 ITC PC 0 00000H CBH DDH EDH FDH INT0 0 ...
Page 98
DDCBH NMI NMI FDCBH ITC UFO 0 PC-1 UFO 1 PC NMI 0 NMI 0 RETN ...
Page 99
...
Page 100
RETN NMI f 0066H IE-RET DI-RET RETN NMI ...
Page 101
38H PC EI ITC 1 RST PC IEF1 ...
Page 102
RST 0 10H 20H 30H IM 1 FFH RST PC 0038H RST 38H ...
Page 103
ISR interrupt vector ISR ...
Page 104
...
Page 105
IL: 33H ...
Page 106
INT2 Sense/Unlatch INT1 Mode Select INT2 Sense/ Unlatch DF INT2 INT1 Mode Sense/ Select Unlatch 1 DCD0 INT2 ...
Page 107
INT1 Mode Select INT2 Mode Select INT1 11 INT1 INT1 1 INT2 ...
Page 108
DCD0 1 CCR DCD0 DCD0 DCD0 CCR ...
Page 109
EI PC 00000 00001 00011 EI ITC 1 IL 00010 ...
Page 110
EI asserted 1 EI ...
Page 111
RETI RET RETI IUS ...
Page 112
RET RET IUS RET OMCR IUS RETI EI RETI EI RETI 0000H FFFFH 00000H RETI RETI FFFFFH ...
Page 113
00000H ...
Page 114
...
Page 115
...
Page 116
CBAR CBAR CBAR CBAR CBR BBR CBR BBR ...
Page 117
...
Page 118
...
Page 119
CBR 0 CBAR 3AH CBR ...
Page 120
BBR 0 BBR:39H CBAR CBR CBR: 39H BBR BBR CBAR ...
Page 121
CBR CBAR CBAR CBR BBR 00000H FFFFFH CBAR CBR BBR 00000H 1 0 0000H FFFFH 0 ...
Page 122
...
Page 123
RCR RCR RCR 36H ...
Page 124
REFE 0 REFE 1 REFW) 0 REFW ...
Page 125
RCR ...
Page 126
...
Page 127
...
Page 128
OUT ...
Page 129
BCR0 SAR0 DAR0 ...
Page 130
IAR1 SAR0 DAR0 MAR0 IAR1 xxRnB xxRnH xxRnL DMODE BCR1 xxRnL xxRnB DSTAT DCNTL MAR1 ...
Page 131
SAR0 20H DAR0 23H BCR0 26H n 1 MAR1 28H 22H 25H 27H n 2AH ...
Page 132
IAR1 2BH IAR1B IAR1B 2DH 0 ...
Page 133
IAR1B: 2DH OUT 1 channel-end DE1 1 0 DE0 0 ...
Page 134
TOUT/ OUT DREQ 1 OUT OUT OUT BCR1 2EH 2FH DSTAT DSTAT ...
Page 135
DWE1 DWE0 1 1 DWE1 DWE0 DSTAT: 30H BCR1 ...
Page 136
...
Page 137
DMODE: 31H ...
Page 138
...
Page 139
...
Page 140
...
Page 141
DCNTL: 32H ...
Page 142
OUT OUT ...
Page 143
0 ...
Page 144
DAR0 SAR0 ...
Page 145
DE0 1 DSTAT DSTAT OUT DMODE DCNTL 0 DIE0 1 ...
Page 146
OUT f f ...
Page 147
SAR0 OUT DSTAT DAR0 DMODE BCR0 DCNTL ...
Page 148
OUT OUT DSTAT ...
Page 149
IAR1 IAR1 DCNTL DSTAT 1 DSTAT MAR1 IAR1B DCNTL 0 ...
Page 150
WSGCS OUT ...
Page 151
DSTAT ...
Page 152
DSTAT 1 IE ...
Page 153
DSTAT DMODE MAR1 IAR1 DMODE 1 DCNTL SAR DAR0 BCR0 BCR1 ...
Page 154
...
Page 155
• • • • • • • • • • • • • ...
Page 156
• • • ...
Page 157
...
Page 158
TSRI TDR1 TSRO TDR TSR TDR0 TSR TDR TSR TSR ...
Page 159
RDR0 RDR1 RDR STAT0 RSR RSR STAT1 ...
Page 160
RDR 1 0 CNTLA 0 ...
Page 161
CNT1LA CNTLB 0 CNTRLA 0 0 CNTLA 0 ASCI0 ...
Page 162
ASEXT0 TDR TDR TDR TDR 0 1 STAT0 0 STAT1 TDR 0 TSR 1 0 ASEXT0 IER0 0 IER0 0 TDR 1 ASEXT0 1 1 ...
Page 163
STAT0 CNTLA0 CNTLA1 STAT1 ...
Page 164
CNTLB 1 CNTLB ...
Page 165
CNTLA1 0 1 ...
Page 166
CNTLB 1 ASEXT 0 ...
Page 167
CNTLA1 CNTLA0 ...
Page 168
CNTLB1 (CNTLB0: 02H CNTLB0 CNTLA 1 ...
Page 169
CNTLB0 0 0 ASEXT CNTLB0 CNTLA ASEXT0 CNTLB1 0 111 0 ...
Page 170
ASEXT 0 111 ASEXT 111 ASEXT 0 1. 111 0 ...
Page 171
CNTLB1 CNTLB0 ACEXT0 ASEXT1 ...
Page 172
IER STAT0 0 STAT0 0 0 CNTLB0 (ASEXT0: 12H TDRE 1 ...
Page 173
CNTLB 111 111 ...
Page 174
CNTLA CNTLA ASEXT IOSTOP 1 (ASEXT1: 13H) ASEXT1 ASEXT0 111 ...
Page 175
ASEXT CNTLA (ASTC0L: 1AH) (ASTC1L: (ASTC0H: 1BH) (ASTC1H: ...
Page 176
Sampling Rate ASEXT 0 bits/second = fPHI/ ((10+20*PS) *2^SS2-0 *Sampling Rate) fCKAout = fPHI/((10+20*PS)*2^SS2..SS0 (fPHI/(2*bits/second*Sampling Rate CNTLA 111 111 ...
Page 177
Rate) fCKAout = fPHI/(2*(TC+2)) 111 1 ...
Page 178
ASEXT0 0 ASEXT0 0 1 STAT0 0 CNTLB0 0 0 STAT0 0 STAT0 STAT0 ...
Page 179
...
Page 180
STAT 1 ASEXT 1 / ASEXT 1 ASEXT 1 ...
Page 181
0 ...
Page 182
...
Page 183
• • • • • 1 ...
Page 184
(TRDR:0BH) ...
Page 185
(CNTR:0AH ...
Page 186
...
Page 187
0 1 ...
Page 188
...
Page 189
...
Page 190
...
Page 191
...
Page 192
...
Page 193
IAR1B 1 OUT 0 OUT ...
Page 194
FFFFH TMDR 0 RLDR TMDR TMDRnL TMDRnH TMDRnL TMDRnH TMDR TMDR TMDR TMDR TCR TMDR TDE TMDR TMDR ...
Page 195
I/O Address = CH0, OEH, OFH, CH1: 16H, 17H) RLDR1 RLDR0L RLDR1H RLDR1L FFFFH TMDR RLDR RLDR RLDR0 RLDR0 RLDR1 0 RLDR0H ...
Page 196
TCR (TCR: 10H TCR 0 0 TCR ...
Page 197
OUT 1 OUT 0 1 OUT 0 OUT PVU PVU ...
Page 198
287 ...
Page 199
TCR FFFFH TMDR TMDRnL TMDR RLDRnL TCR TMDR RLDR TMDRnH RLDRnH ...
Page 200
TMDR RLDR TMDR RLDR 0 1 TMDR ...