Z8018233FSC1838TR Zilog, Z8018233FSC1838TR Datasheet - Page 19
Z8018233FSC1838TR
Manufacturer Part Number
Z8018233FSC1838TR
Description
IC Z180 MPU 100QFP
Manufacturer
Zilog
Datasheet
1.Z8018233FSG.pdf
(109 pages)
Specifications of Z8018233FSC1838TR
Processor Type
Z180
Features
Smart Peripheral Controller
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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The following features are common to both the ESCC and
the CMOS SCC:
DS971820600
Zilog
Two independent full-duplex channels
Synchronous/Isochronous data rates:
Asynchronous capabilities
- 5, 6, 7 or 8 bits/character (capable of handling
- 1, 1.5, or 2 stop bits
- Odd or even parity
- Times 1, 16, 32 or 64 clock modes
- Break generation and detection
- Parity, overrun and framing error detection
Byte oriented synchronous capabilities:
SDLC/HDLC capabilities:
- Up to 1/4 of the PCLK using external clock source
- Up to 5 Mbits/sec at 20 MHz PCLK (ESCC).
- Internal or external character synchronization
- One or two sync characters (6 or 8 bits/sync
- Automatic Cyclic Redundancy Check (CRC)
- Abort sequence generation and checking
- Automatic zero insertion and detection
- Automatic flag insertion between messages
- Address field recognition
- I-field residue handling
- CRC generation/detection
- SDLC loop mode with EOP recognition/loop entry
4 bits/character or less)
character) in separate registers
generation/detection
and exit
PS009801-0301
P R E L I M I N A R Y
The following features are implemented in the ESCC
the Z80182/Z8L182 only:
Note: The ESCC
programmed to divide-by-two mode when operating above
the following conditions:
NRZ, NRZI or FM encoding/decoding. Manchester
Code Decoding (Encoding with External Logic).
Baud Rate Generator in each Channel
Digital Phase-Locked Loop (DPLL) for Clock Recovery
Crystal Oscillator
New 32-bit CRC-32 (Ethernet Polynomial)
ESCC Programmable Clock
- programmed to be equal to system clock
- programmed by Z80182 Enhancement Register
divided by one or two
– PHI > 20 MHz at 5.0V
– PHI > 10 MHz at 3.0V
™
programmable clock must be
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
3-19
™
for
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