Z85C3016VSG Zilog, Z85C3016VSG Datasheet - Page 44

IC 16MHZ Z8500 CMOS SCC 44-PLCC

Z85C3016VSG

Manufacturer Part Number
Z85C3016VSG
Description
IC 16MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Datasheets

Specifications of Z85C3016VSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3938
Z85C3016VSG

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CMOS SCC Serial Communications Controller
Product Specification
40
Interrupt Acknowledge Cycle Timing
Figure 26
displays the Interrupt Acknowledge cycle timing. The address on AD7–AD0
and the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is
Low, the address and CS0 are ignored. The state of the R/W and CS1 are also ignored for
the duration of the Interrupt Acknowledge cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an
interrupt pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was
intended for the SCC. In this case, the SCC is programmed to respond to RD Low by
placing its interrupt vector on D7-D0 and internally setting the appropriate Interrupt-
Under-Service latch.
AS
CS0
(Ignored)
INTACK
AD7–AD0
(Ignored)
Vector
DS
Figure 26. Interrupt Acknowledge Cycle Timing
PS011705-0608
Functional Description

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