IDT79RC32V334-150BBI8 IDT, Integrated Device Technology Inc, IDT79RC32V334-150BBI8 Datasheet - Page 10

• Manufacturer Part Number: IDT79RC32V334-150BBI8
• Description: IC PROC 32BIT CORE 150MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V334-150BBI8

• Processor Type: RISC 32-Bit
• Speed: 150MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32V334-150BBI8

cpu_dt_r_n
JTAG Interface Signals
jtag_tck
jtag_tdi,
ejtag_dint_n
jtag_tdo,
ejtag_tpc
jtag_tms
jtag_trst_n
ejtag_dclk
ejtag_pcst[2:0]
ejtag_debugboot
ejtag_tms
IDT 79RC32334—Rev. Y
Name
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
I/O
Status
Reset
State
Z
Z
Z
Z
L
Capability
external pull-
external pull-
Strength
Requires
Requires
Drive
down
High
Low
—
—
up
—
—
—
—
—
—
CPU Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during
read operations.
1st Alternate function: mem_245_dt_r_n.
2nd Alternate function: sdram_245_dt_r_n.
JTAG Test Clock
Requires external pull-down.
An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of
the system and the processor clock with nominal 50% duty cycle.
JTAG Test Data In
Requires an external pull-up on the board.
On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register,
depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the
debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG).
This pin is also used as the ejtag_dint_n signal in the EJTAG mode.
JTAG Test Data Out
The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. When
no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-
sequential program counter at the processor clock or at a division of processor clock. This pin is also used
as the ejtag_tpc signal in the EJTAG mode.
JTAG Test Mode Select
Requires external pull-up.
The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.
jtag_tms is sampled on the rising edge of the jtag_tck.
JTAG Test Reset
When neither JTAG nor EJTAG are being used, jtag_trst_n must be driven low (pulled down) or the
jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked.
EJTAG Test Clock
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the
ejtag_tpc signal at the processor clock speed or any division of the internal pipeline.
EJTAG PC Trace Status Information
111 (STL) Pipe line Stall
110 (JMP) Branch/Jump forms with PC output
101 (BRT) Branch/Jump forms with no PC output
100 (EXP) Exception generated with an exception vector code output
011 (SEQ) Sequential performance
010 (TST) Trace is outputted at pipeline stall time
001 (TSQ) Trace trigger output at performance time
000 (DBM) Run Debug Mode
Alternate function: modebit[2:0].
EJTAG DebugBoot
The ejtag_debugboot input is used during reset and forces the CPU core to take a debug exception at the
end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe
without having the external memory working. This input signal is level sensitive and is not latched inter-
nally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].
EJTAG Test Mode Select
An external pull-up on the board is required.
The ejtag_tms is sampled on the rising edge of jtag_tck.
Table 1 Pin Description (Part 6 of 7)
10 of 30
Description
August 31, 2004