IDT79RC32V334-100BBI IDT, Integrated Device Technology Inc, IDT79RC32V334-100BBI Datasheet - Page 4
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IDT79RC32V334-100BBI
Manufacturer Part Number
IDT79RC32V334-100BBI
Description
IC PROC 32BIT CORE 100MHZ 256BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Interprise™r
Datasheet
1.IDT79RC32V334-100BB8.pdf
(30 pages)
Specifications of IDT79RC32V334-100BBI
Processor Type
RISC 32-Bit
Speed
100MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
79RC32V334-100BBI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT79RC32V334-100BBI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Packaging
1.0mm ball spacing.
Thermal Considerations
guaranteed in an ambient temperature range of 0° to +70° C for
commercial temperature devices; -40° to +85° for industrial temperature
devices.
Revision History
changed cpu_dr_r_n pin from Input to Output. Updated document from
Advance to Preliminary Information.
debug_cpu_dma_n signal. In the AC Timing Characteristics table,
added SPI section and adjusted parameters in the Reset section.
information regarding external pull-ups and pull-downs to the Pin
Description Table. Made minor revisions in other parts of the data sheet.
ground pins. Revised Power Curves section to reflect support of only 2x,
3x, and 4x.
Consumption table. Extended Power Curve figure to 75 MHz.
Local System Interface section of Table 6, changed Thld2 values for
mem_data[31:0] from 1.8 to 1.5 ns and changed Tdoh3 values for
mem_addr[25:2], etc. from 1.8 to 1.5 ns.
period in Table 5 and added footnote. In Table 1, added 2nd alternate
function for spi_mosi, spi_miso, spi_sck. In Table 10, removed the “1”
from Alt column for cpu_masterclk and added “2” in Alt column for pins
G3, G4, H2. In RC32334 Alternate Signal Functions table: added pin T2;
added pin names in Alt #2 column for pins G3, G4, H2; added PIO[11] to
Alt #2 column for pin R3.
values for Tsu9 from the Max to the Min columns.
and commercial uses from +70° C to +85° C.
output_clk category and added NA to Min and Max columns. In Figure 3
(Reset Specification), enhanced signal line for cpu_masterclk. In Local
System Interface section of AC Timing Characteristics table, changed
values in Min column for last category of signals (Tdoh3) from 1.5 to 2.5
for all speeds. In SDRAM Controller section of same table, changed
values in Min column for last category of signals (9 signals) from 1 to 2.5
for all speeds.
IDT 79RC32334—Rev. Y
The RC32334 is packaged using a 256-lead PBGA package, with
The RC32334 consumes less than 2.1 W peak power. The device is
May 16, 2000: Initial version.
June 8, 2000: In CPU Core Specific Signals section of Table 1,
June 15, 2000: In Table 1, switched assertion and de-assertion for
July 12, 2000: Removed “Preliminary Information” statement. Added
August 3, 2000: Added Pin Layout diagram showing power and
August 30, 2000: Added Standby mode and values to Power
September 25, 2000: Changed MIPS32 ISA to Enhanced MIPS-II. In
December 12, 2000: Changed Max values for cpu_masterclock
January 4, 2001: In Table 6 under Interrupt Handling, moved the
March 13, 2001: Changed upper ambient temperature for industrial
June 7, 2001: In the Clock Parameters table, added footnote 3 to
4 of 30
mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10;
switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and
Thld22; moved ejtag_pcst[2:0] from Reset to Debug Interface category
under Tsu20 and Thld20.
2 footnotes to Table 10.
Characteristics table, changed values in Min column for last category of
signals (Tdoh3) from 2.5 to 1.5 for all speeds. In Table 8, PCI Drive
Output Pads, the Conditions for parameters V
changed to read Per PCI 2.2.
uses back from +85° C to +70° C (changed erroneously from 70 to 85
on March 13, 2001). Added Reset State Status column to Table 1.
Revised description of jtag_trst_n in Table 1 and changed this pin to a
pull-down instead of a pull-up.
no longer applicable to revision Z.
from 1 to zero; DMA section, changed Thld9 Min values from 2 to 1; in
PIO section, changed Thld9 Min values from 2 to 1; in Timer section,
changed Thld10 Min values from 2 to 1. Revision Y data sheet changed
from Preliminary to Final.
Clock Parameters. Added mem_addr[16] and sdram_addr[16] to Tables
1 and 12. Changed Logic Diagram to include sdram_addr[16].
Characteristics, setup and hold time categories for cpu_coldreset_n
have been deleted.
Input Pads, and All Pads) and added footnotes 2 and 3.
for pci_rst_n. Specified “cold” reset on pages 11 and 12. Changed the
maximum value for Vcc to 4.0 in Table 10, Absolute Maximum Ratings,
and changed footnote 1 to that table. Added Power Ramp-up section on
page 21.
September 14, 2001: In the Reset category of Table 6: switched
November 1, 2001: Added Input Voltage Undershoot parameter and
March 20, 2002: In Local System Interface section of AC Timing
May 2, 2002: Changed upper ambient temperature for commercial
July 3, 2002: This data sheet now describes revision Y silicon and is
July 12, 2002: In Table 6: PCI section, changed Thld Min values
September 18, 2002: Added cpu_coldreset_n rise time to Table 5,
December 18, 2002: In the Reset section of Table 6, AC Timing
July 30, 2003: In Table 8, added 3 new categories (Input Pads, PCI
August 31, 2004: Added ”Green” orderable parts on page 30.
March 24, 2004: In Table 1, changed description in Satellite Mode
OL
, V
OH
August 31, 2004
, V
IL
, and V
IH
were