IDT79RC32T351-133DH IDT, Integrated Device Technology Inc, IDT79RC32T351-133DH Datasheet - Page 9

• Manufacturer Part Number: IDT79RC32T351-133DH
• Description: IC MPU 32BIT CORE 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T351-133DH

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T351-133DH

MIIMDIOP
MIIRXCLKP
MIIRXDP[3:0]
MIIRXDVP
MIIRXERP
MIITXCLKP
MIITXDP[3:0]
MIITXENP
MIITXERP
EJTAG
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
EJTAG_PCST[0]
EJTAG_PCST[1]
EJTAG_PCST[2]
EJTAG_DCLK
IDT 79RC32351
Name
Type I/O Type
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Low Drive
Low Drive MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
Low Drive MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission.
Low Drive MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols
Low Drive JTAG Data Output. This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
Low Drive PC trace clock. This is used to capture address and data during EJTAG/ICE mode. EJTAG/ICE enable is selected during
with STI
STI
STI
STI
STI
STI
STI
STI
STI
MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the
ethernet PHY.
MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data.
MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.
MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus.
MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-
rently being sent in the MII receive data bus.
MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data.
which are not valid data or delimiters.
JTAG Clock. This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an
external resistor, listed in Table 14.
JTAG Data Input. This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,
listed in Table 14. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to
switch the PC trace mode off.
signal is tri-stated. This signal requires an external resistor, listed in Table 14. This is also used to output the EJTAG_TPC
during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.
JTAG Mode Select. This input signal is decoded by the tap controller to control test operation. This signal requires an
external resistor, listed in Table 14.
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[10].
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11].
1st Alternate function: UART channel 1 data set ready, U1DSRN.
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[12].
1st Alternate function: UART channel 1 request to send, U1RTSN.
reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires
an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[13].
1st Alternate function: UART channel 1 clear to send, U1CTSN.
Table 1 Pin Descriptions (Part 5 of 7)
9 of 42
Description
May 25, 2004