IDT79RC32T355-133DH IDT, Integrated Device Technology Inc, IDT79RC32T355-133DH Datasheet - Page 18

• Manufacturer Part Number: IDT79RC32T355-133DH
• Description: IC MPU 32BIT CORE 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T355-133DH

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T355-133DH

IDT 79RC32355
1.
2.
3.
4.
5.
MDATA[31:0]
Mem Control Signals
COLDRSTN
1.
2.
3.
4.
5.
6.
7.
8.
SYSCLKP
BOEN[0]
Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32355 asserts RSTN output low in response.
The RC32355 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc.
The RC32355 deasserts RSTN.
The RC32355 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input.
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.
BDIRN
RSTN
CLKP
MDATA[31:0]
COLDRSTN asserted by external logic.
The RC32355 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response.
External logic begins driving valid boot configuration vector on the data bus, and the RC32355 starts sampling it.
External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is deas-
serted. The RC32355 stops sampling the boot configuration vector.
The RC32355 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high.
SYSCLKP may be held constant after this point if Hold SYSCLKP Constant is selected in the boot configuration vector.
RSTN negated by RC32355.
CPU begins executing by taking MIPS reset exception, and the RC32355 starts sampling RSTN as a warm reset input.
COLDRSTN
RSTN
CLKP
1
>= 100 ms
Tdo2
Active
1
2
Tpw1
2
3
BOOT VECT
>=10ms
*
Figure 7 Warm Reset AC Timing Waveform
Figure 6 Cold Reset AC Timing Waveform
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
*
Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
4
Trise1
Thld3
18 of 47
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
5
*
Deasserted
6
3
4
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
(RSTN ignored during this period
to allow pull-up to drive signal high)
*
FFFF_FFFF
7
FFFF_FFFF
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
5
Active
*
8
May 25, 2004