IDT79RC64T575-250DP IDT, Integrated Device Technology Inc, IDT79RC64T575-250DP Datasheet - Page 5

• Manufacturer Part Number: IDT79RC64T575-250DP
• Description: IC MPU 64BIT EMB 250MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC64T575-250DP

• Processor Type: RISC 64-Bit
• Speed: 250MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC64T575-250DP

cache line block transaction requires 4 double word data cycles or 8
single word cycles as well as whether a single data transfer—larger than
4 bytes—must be divided into two smaller transfers.
SysClock cycles and is activated and controlled through mode bit
(17:15) settings selected during the reset initialization sequence. The
‘000’ setting provides the same write operations timing protocol as the
RC4640, RC4650, and RC5000 processors.
interface is enhanced during write cycles with a programmable delay
that is inserted between the write address and the write data (for both
block and non-block writes).
full JTAG boundary scan facility. Five pins—TDI, TDO, TMS, TCK,
TRST*—have been incorporated to support the standard JTAG inter-
face.
that are based on IDT’s RC4640/RC4650 and RC64474/RC64475
processors
software and bus protocol compatibility ensures the RC64574/575
processors access to an existing market and development infrastruc-
ture, allowing quicker time to market.
Development Tools
Development Tools
Development Tools
Development Tools
designers in the rapid development of RC64574/575 based systems.
This accessibility allows a wide variety of customers to take full advan-
tage of the device’s high-performance features while addressing today’s
aggressive time-to-market demands.
Cache Memory
Cache Memory
Cache Memory
Cache Memory
operating efficiently, on-chip instruction and data caches have been
incorporated. Each cache has its own data path and can be accessed in
the same single pipeline clock cycle.
indexed, physically tagged, and word parity protected. Because this
cache is virtually indexed, the virtual-to-physical address translation
occurs in parallel with the cache access, further increasing performance
by allowing both operations to occur simultaneously. The instruction
cache provides a peak instruction bandwidth of 2GB/sec at 250MHz.
protected and has a fixed 32-byte (eight words) line size. Its tag is
protected with a single parity bit. To allow simultaneous address transla-
tion and data cache access, the D-cache is virtually indexed and physi-
cally tagged. The data cache can provide 8 bytes each clock cycle, for a
peak bandwidth of 2GB/s.
79RC64574™ 79RC64575™
Choosing a 32- or 64-bit wide system interface dictates whether a
As shown in Table 3, the bus delay can be defined as 0 to 7
To facilitate discrete interface to SyncDRAM, the RC64574/575 bus
Board-level testing during Run-Time mode is facilitated through the
The RC64574/575 devices offer a direct migration path for designs
An array of hardware and software tools is available to assist system
To keep the high-performance pipeline of the RC64574/575 full and
The 32kB two-way set associative instruction cache is virtually
The 32kB two-way set associative data cache is byte parity
2.
To ensure socket compatibility, refer to Table 8 and Table 9.
2
, through full pin and socket compatibility. Full 64-bit-family
5 of 28
access, a per line “cache locking” feature has been implemented.
Once enabled, a cache is said to be locked when a particular piece of
code or data is loaded into the cache and that cache location will not be
selected later for refill by other data.
Power Management
Power Management
Power Management
Power Management
Standby mode. The internal clocks will shut down, thus freezing the
pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*,
NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. Once in
Standby Mode, any interrupt, including the internally generated timer
interrupt, will cause the CPU to exit Standby Mode.
Thermal Considerations
Thermal Considerations
Thermal Considerations
Thermal Considerations
uses a 32-bit external bus, offering the ideal combination of 64-bit
processing power and 32-bit low-cost memory systems. The RC64575
is packaged in a 208-pin QFP footprint package and uses the full 64-bit
external bus. The RC64575 is ideal for applications requiring 64-bit
performance and 64-bit external bandwidth.
+85 C for commercial temperature devices and -40 to +85 C for
Industrial temperature devices. Package type, speed (power) of the
device, and air flow conditions affect the equivalent ambient temperature
conditions that will meet these specifications.
given package, the equivalent allowable ambient temperature, T
be calculated. The following equation relates ambient and case temper-
atures:
calculated by using the maximum I
Typical values for
that the RC64574/575 processor implements advanced power manage-
ment, which substantially reduces the typical power dissipation of the
device.
Revision History
Revision History
Revision History
Revision History
128 QFP
208 QFP
Airflow (ft/min)
To lock critical sections of code and/or data into the caches for quick
Executing the WAIT instruction enables the processor to enter
The RC64574 is packaged in a 128-pin QFP footprint package and
Using the thermal resistance from case to ambient (
T
where P is the maximum power consumption at hot temperature,
July 22, 1999: Original data sheet.
Both devices are guaranteed in a case temperature range of 0 to
A
= T
Table 4 Thermal Resistance ( CA) at Various Airflows
C
- P *
CA
CA
16
20
at various air flow are shown in Table 4. Note
0
10
13
200
CC
9
10
400
specification for the device.
CA
7
9
December 14, 2001
600
6
8
800
CA
1000
5
7
) of the
A
, can