IDT79R4700-100G IDT, Integrated Device Technology Inc, IDT79R4700-100G Datasheet - Page 2

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IDT79R4700-100G

Manufacturer Part Number
IDT79R4700-100G
Description
IC MPU 64BIT 5V 100MHZ 179-PGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT79R4700-100G

Processor Type
RISC 64-Bit
Speed
100MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
79R4700-100G

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47
and architecture. A more detailed description of this processor is
provided in the IDT79R4700 RISC Processor Hardware User’s Manual,
available from Integrated Device Technology (IDT). Information on
development support, applications notes and complementary products
is available on the IDT Web site www.idt.com or through your local IDT
sales representative.
device, the R4700 indicates a 5V part; RV4700 designates a reduced
voltage (3V) part; and the RC4700 reflects either.
Hardware Overview
designed for high-performance computing. The R4700’s key elements
are briefly described below. A more detailed explanation of each
subsystem is available in the user’s manual.
Pipeline
structure implemented in the IDT79R32364. This pipeline’s simplicity
allows the RC4700 to be lower cost and lower power than super-scalar
or super-pipelined processors. The pipeline stages are shown in Figure
3 on page 3.
Integer Execution Engine
is upwardly compatible with applications that run on earlier generation
parts.
tions, better code density, greater multi-processing support, improved
performance for commonly used code sequences in operating system
kernels and faster execution of floating-point intensive applications. All
0
IDT79R4700
This data sheet provides an overview of the R4700’s CPU features
Note: Throughout this data sheet and any other IDT materials for this
The RC4700 processor family brings a high-level of integration
The RC4700 uses a simple 5-stage pipeline, similar to the pipeline
The R4700 implements the MIPS-III Instruction Set architecture and
Implementation of the MIPS-III architecture results in 64-bit opera-
PageMask
EntryHi
10*
5*
* Register number
(entries protected
from TLBWR)
TLB
EntryLo1
EntryLo0
2*
3*
3*
Figure 1 The RC4700 CPO Registers
Random
Index
Wired
0*
1*
6*
BadVAddr
Context
Count
Status
TagHi
EPC
PRId
ECC
12*
14*
15*
29*
26*
8*
9*
4*
Compare
XContext
ErrorEPC
CacheErr
LLAddr
TagLo
Cause
Config
13*
30*
16*
27*
11*
20*
17*
28*
2 of 25
resource dependencies are made transparent to the programmer,
insuring transportability among implementations of the MIPS instruction
set architecture.
single cycle ALU operations (logical, shift, add, sub) and an autono-
mous multiply/divide unit. Register resources include:
registers and a floating-point control/status register.
Register File
These registers are used for scalar integer operations and address
calculation. The register file consists of two read ports and one write
port and is fully bypassed to minimize operation latency in the pipeline.
ALU
adder performs address calculations in addition to arithmetic operations,
and the logic unit performs all logical and shift operations. Each of these
units is highly optimized and can perform an operation in a single pipe-
line cycle.
Integer Multiply/Divide
the floating-point unit. The results of the operation are placed in the HI
and LO registers. The values can then be transferred to the general
purpose register file using the MFHI/MFLO instructions. To prevent the
General Purpose Registers
63
The MIPS integer unit implements a load/store architecture with
Also, the on-chip floating-point co-processor adds 32 floating-point
The R4700 has 32 general-purpose registers (shown in Figure 2).
The RC4700 ALU consists of the integer adder and logic unit. The
To perform integer multiply and divide operations, the RC4700 uses
32 general-purpose orthogonal integer registers
HI/LO result registers, for the integer multiply/divide unit
Program counter
r29
r30
r31
r1
r2
0
0
Figure 2 R4700 CPU Registers
Multiply/Divide Registers
63
63
63
Program Counter
December 5, 2008
PC
LO
HI
0
0
0

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