IDT79R4700-133DP IDT, Integrated Device Technology Inc, IDT79R4700-133DP Datasheet - Page 4

• Manufacturer Part Number: IDT79R4700-133DP
• Description: IC MPU 64BIT 5V 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R4700-133DP

• Processor Type: RISC 64-Bit
• Speed: 133MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R4700-133DP

occurrence of an interlock or stall, a required number of processor
internal cycles must occur between an integer multiply or divide and a
subsequent MFHI or MFLO operation.
Floating-Point Co-Processor
chip and includes a floating-point register file and execution units. The
floating-point co-processor forms a “seamless” interface with the integer
unit, decoding and executing instructions in parallel with the integer unit.
Floating-Point Units
precision arithmetic, as specified in the IEEE Standard 754. The execu-
tion unit is separated into a multiply unit and a combined add/convert/
divide/square root unit. Overlap of multiplies and add/subtract is
supported. The multiplier is partially pipelined, allowing a new multiply to
begin every four cycles.
allowing both overlapped and pipelined operations. Precise exceptions
are extremely important in mission-critical environments and highly
desirable for debugging in any environment.
subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats and
floating-point compare. These operations comply with the IEEE Stan-
dard 754.
internal processor cycles. Note that multiplies are pipelined so that a
new multiply can be initiated every four pipeline cycles
Floating-Point General Register File
ters. With the LDC1 and SDC1 instructions the floating-point unit can
take advantage of the 64-bit wide data cache and issue a co-processor
load or store doubleword instruction in every cycle.
for determining configuration and revision information for the copro-
cessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
IDT79R4700
The RC4700 incorporates a complete floating-point co-processor on
The RC4700 floating-point execution units support single and double
The RC4700 maintains fully precise floating-point exceptions while
The floating-point unit operation’s set includes floating-point add,
Table 1 lists the latencies of some of the floating-point instructions in
The floating-point register file is made up of thirty-two 64-bit regis-
The floating-point control register space contains two registers: one
MULT
DIV
Operation
32-bit
6 - 9
42
64-bit
7 - 10
74
4 of 25
System Control Co-processor (CP0)
sible for the virtual memory sub-system, the exception control system
and the diagnostics capability of the processor. In the MIPS architec-
ture, the system control co-processor (and thus the kernel software) is
implementation dependent.
System Control Co-Processor Registers
registers, on-chip. These registers (shown in Figure 1 on page 2)
provide the path through which the virtual memory system’s page
mapping is examined and changed, exceptions are handled and oper-
ating modes are controlled (kernel vs. user mode, interrupts enabled or
disabled, cache features). In addition, to aid in cache diagnostic testing
and assist in data error detection, the RC4700 includes registers to
implement a real-time cycle counting facility.
Virtual-to-Physical Address Mapping
provides the user, supervisor, and kernel modes of virtual addressing,
available to system software. Bits in a status register determine which
virtual addressing mode is used.
address space of 256GB (2GB for 32-bit address mode). When oper-
ating in the kernel mode, four distinct virtual address spaces—totalling
1024GB (4GB in 32-bit address mode)—are simultaneously available
and are differentiated by the high-order bits of the virtual address.
The system control co-processor in the MIPS architecture is respon-
The RC4700 incorporates all system control co-processor (CP0)
To establish a secure environment for user processing, the RC4700
While in user mode, the RC4700 provides a single, uniform virtual
ADD
SUB
MUL
DIV
SQRT
CMP
FIX
FLOAT
ABS
MOV
NEG
LWC1, LDC1
SWC1, SDC1
Operation
Table 1 RC4700 Instruction Latencies
Precision
Single
32
31
4
4
4
3
4
6
1
1
1
2
1
Precision
December 5, 2008
Double
61
60
4
4
5
3
4
6
1
1
1
2
1