PRIXP423BB Intel, PRIXP423BB Datasheet - Page 29

• Manufacturer Part Number: PRIXP423BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP423BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869741

33.
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Status:
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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PCI Accesses to the Queue Manager During Queue and SRAM Mode
(SCR 4076)
Under certain data traffic, the PCI controller may generate spurious write transfers and may return
incorrect data on reads when accessing the Queue Manager in SRAM mode. Additionally, if the
Queue Manager is being used in the Queue mode, PCI accesses must not use memory-mapped
registers BAR0-3 since these accesses cause pre-fetches during reads.
Pre-fetches will cause Queue data to be lost.
Do not use the Queue Manager's SRAM mode during PCI accesses. Instead use the SDRAM
memory space when generating PCI accesses to the IXP42X product line memory space. An
external PCI master must use PCI BAR5 when accessing the Queue Manager when in Queue
mode.
No
Ethernet MACs Detect Late Collision Earlier Than Ethernet 802.3
Specifications (SCR 4062)
On an improperly designed network, when a collision occurs on the threshold of the smallest valid
Ethernet frame, it is detected as a late collision rather than an early collision.
The collided frame will not be retried up to the programmed retry count and will be dropped.
Cable lengths, number of repeaters, and other parameters that affect the network design need to be
planned to not operate on the boundary of the Ethernet specifications.
No
Read of PCI Controllers BAR 32'hXXFF_FFFC Rd[N] Corrupts
Subsequent Rd[N+1] (SCR 3850)
If specifically reading the ‘last word’ address of a BAR register, read(n), and if that BAR register is
set up adjacent to undefined memory space (that is, not adjacent to another BAR register), this
read(n) will complete correctly, but will cause data corruption in the subsequent read(n+1).
Upon the next subsequent external PCI master read Rd[N+1], the PCI controller returns incorrect
read data of Rd[N].
Avoid reading the last word of the BAR or avoid reading this one BAR entirely. Perhaps change the
setup such that the BAR registers are adjacent to each other in memory space and place the config
BAR 4 on top of the final BAR so that no ‘last word’ address in each memory address BAR0-3 is
adjacent to undefined memory space. For example:
BAR4 - config BAR: highest address
BAR3
BAR2
BAR1
BAR0 - lowest address
No
Fix.
Fix.
Fix.
Non-Core Errata
29