KU80960CA25 Intel, KU80960CA25 Datasheet - Page 11

• Manufacturer Part Number: KU80960CA25
• Description: IC MPU I960CA 5V 25MHZ 196QFP
• Manufacturer: Intel

Specifications of KU80960CA25

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: CA suffix, 32-Bit with DMA
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 196-QFP
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 802900

BOFF
HOLDA
BREQ
D/C
DMA
SUP
Name
Type
R(Q)
H(Q)
H(Z)
R(Z)
H(1)
R(0)
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
S(L)
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 3 of 3)
O
O
O
O
O
S
S
S
S
S
I
BUS BACKOFF, when asserted, suspends the current access and causes the bus
pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock
cycle and the access is resumed.
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relin-
quished control of the external bus. When HOLDA is asserted, the external address
bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ
are used together to arbitrate access to the processor’s external bus by external bus
agents. Since the processor grants HOLD requests and enters the Hold Acknowledge
state even while RESET is asserted, the state of the HOLDA pin is independent of the
RESET pin.
BUS REQUEST is asserted when the bus controller has a request pending. BREQ
can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to
determine when to return mastership of the external bus to the processor.
DATA OR CODE is asserted for a data request and deasserted for instruction
requests. D/C has the same timing as W/R.
DMA ACCESS indicates whether the bus request was initiated by the DMA controller.
DMA is asserted for any DMA request. DMA is deasserted for all other requests.
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode. SUP is asserted when the request has supervisor privileges and is
deasserted otherwise. SUP can be used to isolate supervisor code and data
structures from non-supervisor requests.
Description
80960CA-33, -25, -16
7