GCIXP1200GA Intel, GCIXP1200GA Datasheet - Page 8

• Manufacturer Part Number: GCIXP1200GA
• Description: IC MPU NETWORK 166MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GA

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 166MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839427

Intel
Summary Table of Changes
Errata
8
®
IXP1200 Network Processor
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Steppings
B0
X
X
X
X
X
X
X
X
X
X
X
C0
X
X
X
X
X
X
X
X
D0
X
X
X
X
X
X
X
Page
12
12
12
13
13
13
14
14
14
15
15
15
15
16
16
16
16
16
17
17
17
17
18
18
18
18
18
19
19
19
20
Status
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
SRAM Registers
CSR Access Using PCI Memory Cycles
Spurious SDRAM Parity Errors
DMA Write Data Concurrency
I
PCI_DMA Instruction
SDRAM Memory Reference with SDRAM
optimize_ mem Instruction Qualifier
SRAM Memory Reference with SRAM
optimize_ mem Instruction Qualifier
Clock Synchronization Differences Between
StrongARM* Core and IX Bus Clock
Data Transfers on Multiword PCI Target
Read and DMA Transfers
PCI Performance
Packet Status Length
Clock Setup Time
FDAT and FBE# Signals After Reset
Flow Control Data
Sixteen Quadword Transfers With SDRAM
Instruction
BIST
Internal Arbiter
Burst Lengths Exceeding One Page
Cache Line Size of 0
PCI Bus at Frequencies Less than 33 MHz
Prepend in 32-Bit Unidirectional IX Bus
Mode
PCI CBE# Values on I/O Reads
Deleted. Included in Errata 12.
PCI Extended Capabilities Support
Detection
Flow-Thru SRAM Read-Modify-Write
Hold Time Issues for all PCI Signals (Both
Bused and Control)
Non-aligned PCI DMA Transfers
SDRAM Memory Configuration.
IX Bus Contention in Shared IX Bus Mode
Tval max Timing Issues When Running at
66 MHz for all PCI Signals
2
O Counter Data Concurrency
ERRATA
Specification Update