XS1-L01A-TQ128-I4 XMOS, XS1-L01A-TQ128-I4 Datasheet - Page 12

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XS1-L01A-TQ128-I4

Manufacturer Part Number
XS1-L01A-TQ128-I4
Description
IC MPU 32BIT SINGLE CORE 128TQFP
Manufacturer
XMOS
Datasheet

Specifications of XS1-L01A-TQ128-I4

Processor Type
XCore 32-Bit
Speed
400MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1003
XS1-L01-TQ128-I4
XS1-L1 128TQFP Datasheet (2.2)
The boundary scan TAP is a standard 1149.1 compliant TAP and can be used for
XCore, Switch and OTP for such actions as loading code and debugging. Both TAPs
which optionally add in additional TAPs into the JTAG chain for each of the Switch,
XCore and OTP. The XCore TAP allows register read/write commands to be made for
A diagram of the JTAG chain structure is shown below:
The JTAG device identification register can be read by using the IDCODE instruction.
boundary scan of the I/O pins of the device. The chip TAP allows access into the
have a bypass register, an instruction register length of 4, a data register length of
32 and a TDO register. From reset, the chip TAP is in BYPASS so simply presents an
extra 1-bit into the scan chain when shifting data.
If access to the XCore/Switch/OTP is required, the ChipTAP sets internal multiplexers
program loading/debug.
3.6.1 Device identification register
Its contents are specified as follows:
TRST_N
TMS
TCK
TDI
IO
IO
IO
TDI
IR_LENGTH = 4
TCK
BS TAP
GLOBAL TRST_N
TMS
TDO
TDI
IR_LENGTH = 4
TCK
CHIP TAP
Switch
XCore
OTP
JTAG
XS1-L1
TMS
TDO
TDO
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