Z85C3008PEC Zilog, Z85C3008PEC Datasheet - Page 38
Z85C3008PEC
Manufacturer Part Number
Z85C3008PEC
Description
IC 8MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Datasheet
1.Z85C3008PSG.pdf
(71 pages)
Specifications of Z85C3008PEC
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3058
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PS011705-0608
Z85C30 Timing
The SCC generates internal control signals from the WR and RD that are related to PCLK.
PCLK has no phase relationship with WR and RD, the circuitry generating the internal
control signals provides time for meta-stable conditions to disappear. This gives rise to a
recovery time related to PCLK. The recovery time applies only between bus transactions
involving the SCC.
The recovery time required for proper operation is specified from the falling edge of WR
or RD in the first transaction involving the SCC to the falling edge of WR or RD in the
second transaction involving the SCC. This time must be at least 3 PCLKs regardless of
which register or channel is being accessed.
The Z85C30 timings are described below:
•
•
•
Read Cycle Timing
Write Cycle Timing
Interrupt Acknowledge Cycle Timing
CMOS SCC Serial Communications Controller
Product Specification
Functional Description
34
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