TN80C188EB13 Intel, TN80C188EB13 Datasheet - Page 27

• Manufacturer Part Number: TN80C188EB13
• Description: IC MPU 16BIT 5V 13MHZ EXT 84PLCC
• Manufacturer: Intel

Specifications of TN80C188EB13

• Rohs Status: RoHS non-compliant
• Processor Type: 80C188
• Features: EB suffix, 16-Bit, Extended Temp
• Speed: 13MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Other names: 803537

I
The current (I
essentially composed of two components I
I
I
device leakage and is measured with all inputs or
floating outputs at GND or V
the device) I
and is typically less than 50 A
I
discharge parasitic device capacitance when chang-
ing logic levels Since I
than I
I
I
the device is operating It is given by the formula
Where V
Measuring C
would be difficult Instead C
the above formula by measuring I
and frequency (see Table 11) Using this C
ue I
quency within the specified operating range
EXAMPLE Calculate the typical I
at 10 MHz 4 8V
CCS
PD
CCS
CC
CCS
CC
is the quiescent current that represents internal
VERSUS FREQUENCY AND VOLTAGE
CC
is related to the voltage and frequency at which
is the switching current used to charge and
PD
I
CC
Power
C
f
I
can be calculated at any voltage and fre-
CCS
I
DEV
e
e
PD
e
I
e
Device operating frequency
I
e
DEV
PD
CCS
can often be ignored when calculating
Device operating voltage (V
e
CC
1 Max C
outputs loaded to 50 pF (including CLKOUT and OSCOUT)
2 Typical C
OSCOUT which are not loaded
e
I
CC
I
CC
Device capacitance
) consumption of the processor is
is equal to the Powerdown current
C
C
V
e
on a device like the 80C186EB
DEV
DEV
e
c
e
4 8
I
I
CCS
Device current
DEV
Parameter
(Device in Reset)
(Device in Idle)
CCS
e
c
DEV
V
e
0 583
2 c
is calculated at
is typically much greater
V
CC
DEV
is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and
c
C
Table 11 Device Capacitance (C
c
(no clock applied to
DEV c
C
CC
CC
is calculated using
10
DEV c
at a known V
when operating
f
28 mA
f
CC
b
40 C all floating outputs driven to V
DEV
)
PD
0 583
0 408
Typ
and
val-
CC
80C186EB 80C188EB 80L186EB 80L188EB
PDTMR PIN DELAY CALCULATION
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset during Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabi-
lized)
To calculate the value of capacitor required to pro-
vide a desired delay use the equation
Where t
EXAMPLE To get a delay of 300
value of C
required Round up to standard (available) capaci-
tive values
The above equation applies to delay times greater
than 10
tance needed to achieve the desired delay A delay
variance of
temperature
tremes In general higher V
perature will decrease delay time while lower V
and or higher temperature will increase delay time
0 682
Max
1 02
C
DEV
e
PD
PD
s and will compute the TYPICAL capaci-
mA V MHz
mA V MHz
) Values
desired delay in seconds
e
a
e
440
Units
voltage
50% or
440
capacitive load on PDTMR in mi-
crofarads
c
CC
t
c
e
NOTE
NOTE
or GND and all
(300
C
and device process ex-
b
PD
25% can occur due to
c
Notes
CC
(5V 25 C)
1 2
1 2
10
and or lower tem-
b
6
)
s a capacitor
e
0 132 F is
CC
27