TN80C188EA20 Intel, TN80C188EA20 Datasheet
TN80C188EA20
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TN80C188EA20 Summary of contents
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... Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata ...
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AND 80L186EA 80L188EA 16-Bit High Integration Embedded Processor CONTENTS INTRODUCTION 80C186EA CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EA PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit DMA Control Unit Chip-Select Unit Refresh Control ...
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NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Figure 1 80C186EA 80C188EA Block Diagram 80C186EA 80C188EA 80L186EA 80L188EA 3 3 ...
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INTRODUCTION Unless specifically noted all references to the 80C186EA apply to the 80C188EA 80L186EA and 80L188EA References to pins that differ between the 80C186EA 80L186EA and the 80C188EA 80L188EA are given in parentheses The ‘‘L’’ in ...
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Crystal Connection NOTE The L C network is only required when using a third-overtone crystal 1 1 80C186EA PERIPHERAL ARCHITECTURE The 80C186EA has integrated several common sys- tem peripherals with a CPU core to create a com- pact yet ...
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PCB PCB Function Offset Offset 00H Reserved 40H 02H Reserved 42H 04H Reserved 44H 06H Reserved 46H 08H Reserved 48H 0AH Reserved 4AH 0CH Reserved 4CH 0EH Reserved 4EH 10H Reserved 50H Timer 0 Count 12H ...
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PCB Function Offset 20H Interrupt Vector 22H Specific EOI 24H Reserved 26H Reserved 28H Interrupt Mask 2AH Priority Mask 2C In-Service 2E Interrupt Request 30 Interrupt Status 32 TMR0 Interrupt Control 34 DMA0 Interrupt Control 36 DMA1 Interrupt Control 38 ...
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Interface (80C186EA Only) The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions Connecting the 80C186EA RESOUT and TEST BUSY pins to the 80C187 ...
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... Leaded Chip Carrier (PLCC) package Shrink Quad Flat Pack (SQFP) and Quad Flat Pack (QFP) pack- age For complete package specifications and infor- mation see the Intel Packaging Outlines and Dimen- sions Guide (Order Number 231369) With the extended temperature range operational ...
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Table 2 Pin Description Nomenclature Symbol S(E) S(L) A(E) A(L) H(1) H(0) H(Z) H(Q) H(X) R(WH) R(1) R(0) R(Z) R(Q) R(X) I(1) I(0) I(Z) I(Q) I(X) P(1) P(0) P(Z) P(Q) ...
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Pin Pin Input Output Name Type Type States CLKIN I A(E) OSCOUT O H(Q) R(Q) P(Q) CLKOUT O H(Q) R(Q) P(Q) RESIN I A(L) RESOUT O H(0) R(1) P(0) PDTMR I O A(L) H(WH) ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States A18 16 O H(Z) A19 S6–A16 R(Z) (A19–A8) P( H(Z) R(Z) P(1) ALE QS0 O H(0) R(0) P(0) BHE O ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States WR QS1 O H(Z) R(Z) P(1) ARDY I A(L) S(L) SRDY I S(L) DEN O H(Z) R(Z) P( H(Z) R(Z) P(X) LOCK O H(Z) ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Name Type Type MCS0 PEREQ I O A(L) MCS1 ERROR MCS2 MCS3 NCS PCS4 0 O PCS5 A1 O H(1) H(X) PCS6 A2 T0OUT O T1OUT T0IN I ...
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PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component Figure 9 depicts the complete 80C186EA 80L186EA pinout (PLCC pack- age) as viewed from the top side ...
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... AD8 (A8 AD0 34 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA NOTES 1 The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 5 68-Lead PLCC Pinout Diagram 16 Name Location Name DRQ0 35 MCS3 NCS ...
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Table 6 QFP (EIAJ) Pin Names with Package Location Address Data Bus Bus Control Name Location Name AD0 64 ALE QS0 AD1 66 BHE (RFSH) AD2 68 S0 AD3 70 S1 AD4 74 S2 AD5 76 RD QSMD AD6 78 ...
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... ARDY 39 40 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA NOTES 1 The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 6 Quad Flat Pack (EIAJ) Pinout Diagram 18 Name Location Name ...
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Table 8 SQFP Pin Functions with Package Location AD Bus Bus Control AD0 1 ALE QS0 AD1 3 BHE (RFSH) AD2 6 S0 AD3 8 S1 AD4 12 S2 AD5 14 RD QSMD AD6 16 WR QS1 AD7 18 ARDY ...
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... Figure 7 Shrink Quad Flat Pack (SQFP) Pinout Diagram NOTES 1 XXXXXXXXD indicates the Intel FPO number 2 Pin names in parentheses apply to the 80C188EA PACKAGE THERMAL SPECIFICATIONS The 80C186EA 80L186EA is specified for operation when T (the case temperature) is within the range ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature Case Temperature under Bias Supply Voltage with Respect Voltage on Other Pins with Respect ...
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DC SPECIFICATIONS (80C186EA 80C188EA) Symbol Parameter V Supply Voltage CC V Input Low Voltage for All Pins IL V Input High Voltage for All Pins IH V Output Low Voltage OL V Output High Voltage OH ...
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DC SPECIFICATIONS (80L186EA 80L188EA) Symbol Parameter V Supply Voltage CC V Input Low Voltage for All Pins IL V Input High Voltage for All Pins IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on ...
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I VERSUS FREQUENCY AND VOLTAGE CC The current (I ) consumption of the processor is CC essentially composed of two components I I CCS I is the quiescent current that represents internal PD device leakage and ...
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AC SPECIFICATIONS AC Characteristics 80C186EA25 80C186EA20 80C186EA13 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C CLKIN High Time CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time CF OUTPUT ...
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AC SPECIFICATIONS (Continued) AC Characteristics 80C186EA25 80C186EA20 80C186EA13 Symbol Parameter SYNCHRONOUS INPUTS T TEST NMI INT3 0 CHIS T1 0IN ARDY T TEST NMI INT3 0 CHIH T1 0IN ARDY T AD15 0 (AD7 0) ARDY ...
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AC SPECIFICATIONS AC Characteristics 80L186EA13 80L186EA8 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time CF OUTPUT CLOCK ...
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AC SPECIFICATIONS AC Characteristics 80L186EA13 80L186EA8 Symbol Parameter SYNCHRONOUS INPUTS T TEST NMI INT3 0 T1 0IN ARDY CHIS T TEST NMI INT3 0 T1 0IN ARDY CHIH T AD15 0 (AD7 0) ARDY SRDY DRQ1 ...
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AC SPECIFICATIONS (Continued) Relative Timings (80C186EA25 20 13 80L186EA13 8) Symbol Parameter RELATIVE TIMINGS T ALE Rising to ALE Falling LHLL T Address Valid to ALE Falling AVLL T Chip Selects Valid to ALE Falling PLLL T Address Hold from ...
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AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 8 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the V ...
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NOTE 20% V Float 80 Figure 10 Output Delay and Float Waveform NOTE RESIN measured to CLKIN not CLKOUT Figure 11 Input Setup and Hold 80C186EA 80C188EA 80L186EA 80L188EA 272432 –10 272432 – ...
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NOTES 1 T for write cycle followed by read cycle DXDL 2 Pin names in parentheses apply to tthe 80C188EA Figure 12 Relative Signal Waveform 32 272432 –12 32 ...
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DERATING CURVES Figure 13 Typical Output Delay Variations Versus Load Capacitance RESET The processor performs a reset operation any time the RESIN pin is active The RESIN pin is actually synchronized before it is presented internally which means that the ...
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Figure 15 Powerup Reset Waveforms 34 34 ...
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Figure 16 Warm Reset Waveforms 35 35 ...
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BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various bus signals to CLKOUT These figures ...
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NOTES 1 During the data phase of the bus cycle A19 S6 is driven high for a DMA cycle 2 Pin names in parentheses apply to the 80C188EA Figure 18 Write Cycle Waveform 80C186EA 80C188EA 80L186EA 80L188EA 272432- ...
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NOTES 1 The processor drives these pins to 0 during Idle and Powerdown Modes 2 Pin names in parentheses apply to the 80C188EA Figure 19 Halt Cycle Waveform 38 272432 –19 38 ...
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NOTES 1 INTA occurs one clock later in Slave Mode 2 Pin names in parentheses apply to the 80C188EA Figure 20 INTA Cycle Waveform 80C186EA 80C188EA 80L186EA 80L188EA 272432 – ...
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NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 21 HOLD HLDA Waveform 40 272432 –21 40 ...
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NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 22 DRAM Refresh Cycle During Hold Acknowledge 80C186EA 80C188EA 80L186EA 80L188EA 272432 – ...
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NOTES 1 Generalized diagram for READ or WRITE 2 ARDY low by either edge causes a wait state Only rising ARDY is fully synchronized 3 SRDY low causes a wait state SRDY must meet setup and ...
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EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions The fol- lowing instruction timings represent the ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV Move e Register to Register Memory Register memory to register Immediate to register ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER (Continued) SEGMENT Segment Override ...
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INSTRUCTION SET SUMMARY Function ARITHMETIC (Continued) IMUL Integer multiply (signed Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer Immediate multiply ...
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INSTRUCTION SET SUMMARY Function LOGIC (Continued) XOR Exclusive or e Reg memory and register to either Immediate to register memory Immediate to accumulator 0 ...
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INSTRUCTION SET SUMMARY Function CONTROL TRANSFER (Continued) RET Return from CALL e Within segment Within seg adding immed ...
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INSTRUCTION SET SUMMARY Function PROCESSOR CONTROL CLC Clear carry CMC Complement carry STC Set carry ...
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... REVISION HISTORY Intel 80C186EA 80L186EA devices are marked with a 9-character alphanumeric Intel FPO number un- derneath the product number This data sheet up- date is valid for devices with an ‘‘A’’ ‘‘B’’ ‘‘C’’ ‘‘D’’ ...