TN80C186EA20 Intel, TN80C186EA20 Datasheet - Page 24

• Manufacturer Part Number: TN80C186EA20
• Description: IC MPU 16-BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intel

Specifications of TN80C186EA20

• Rohs Status: RoHS non-compliant
• Processor Type: 80C186
• Features: EA suffix, 16-Bit, Extended Temp
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Other names: 802799

80C186EA 80C188EA 80L186EA 80L188EA
I
The current (I
essentially composed of two components I
I
I
device leakage and is measured with all inputs or
floating outputs at GND or V
the device) I
and is typically less than 50 A
I
discharge parasitic device capacitance when chang-
ing logic levels Since I
than I
I
I
the device is operating It is given by the formula
Where V
Measuring C
would be difficult Instead C
the above formula by measuring I
and frequency (see Table 11) Using this C
ue I
quency within the specified operating range
EXAMPLE Calculate the typical I
at 20 MHz 4 8V
24
CCS
PD
CCS
CC
CCS
CC
is the quiescent current that represents internal
VERSUS FREQUENCY AND VOLTAGE
CC
I
is related to the voltage and frequency at which
is the switching current used to charge and
CC
PD
Power
C
f
I
can be calculated at any voltage and fre-
e
CCS
I
DEV
e
PD
e
I
I
CCS
Device operating frequency
e
DEV
PD
can often be ignored when calculating
Device operating voltage (V
e
CC
1 Max C
outputs loaded to 50 pF (including CLKOUT and OSCOUT)
2 Typical C
OSCOUT which are not loaded
e
e
I
CC
I
e
) consumption of the processor is
is equal to the Powerdown current
C
C
CC
Device capacitance
on a device like the 80C186EA
V
DEV
DEV
4 8
e
e
c
DEV
Parameter
(Device in Reset)
(Device in Idle)
CCS
I
c
I
CCS
Device current
DEV
e
0 515
is calculated at
is typically much greater
V
e
CC
DEV
is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and
2 c
V
(no clock applied to
c
CC
CC
is calculated using
c
C
20
DEV c
C
at a known V
when operating
DEV c
49 mA
CC
b
Table 11 C
f
40 C all floating outputs driven to V
DEV
)
PD
f
0 515
0 391
Typ
and
val-
CC
DEV
PDTMR PIN DELAY CALCULATION
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset during Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabi-
lized)
To calculate the value of capacitor required to pro-
vide a desired delay use the equation
Where t
EXAMPLE To get a delay of 300
value of C
required Round up to standard (available) capaci-
tive values
The above equation applies to delay times greater
than 10
tance needed to achieve the desired delay A delay
variance of
temperature
tremes In general higher V
perature will decrease delay time while lower V
and or higher temperature will increase delay time
0 905
0 635
Max
Values
440
C
e
PD
PD
s and will compute the TYPICAL capaci-
mA V MHz
mA V MHz
desired delay in seconds
c
e
a
e
Units
voltage
50% or
t
440
capacitive load on PDTMR in mi-
crofarads
e
CC
C
c
PD
NOTE
NOTE
or GND and all
(300
and device process ex-
b
(5V 25 C)
25% can occur due to
c
Notes
CC
1 2
1 2
10
and or lower tem-
b
6
)
s a capacitor
e
0 132 F is
CC
24