A80960CA25 Intel, A80960CA25 Datasheet - Page 39

• Manufacturer Part Number: A80960CA25
• Description: IC MPU I960CA 25MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CA25

• Processor Type: i960
• Features: CA suffix, 32-Bit with DMA, 1K Cache
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 802884

5.0
Table 19 lists the condition of each processor output
pin while RESET is asserted (low).
A31:2
D31:0
BE3:0
W/R
ADS
WAIT
BLAST
DT/R
DEN
LOCK
BREQ
D/C
DMA
SUP
FAIL
DACK3:0
EOP3:0/TC3:0
NOTES:
1. With regard to bus output pin state only, the Hold
Acknowledge state takes precedence over the reset
state. Although asserting the RESET pin will internally
reset the processor, the processor’s bus output pins
will not enter the reset state if it has granted Hold
Acknowledge to a previous HOLD request (HOLDA is
active). Furthermore, the processor will grant new
HOLD requests and enter the Hold Acknowledge state
even while in reset.
For example, if HOLDA is inactive and the processor is
in the reset state, then HOLD is asserted, the proces-
sor’s bus pins enter the Hold Acknowledge state and
HOLDA is granted. The processor will not be able to
perform memory accesses until the HOLD request is
removed, even if the RESET pin is brought high. This
operation is provided to simplify boot-up synchroniza-
tion among multiple processors sharing the same bus.
Pins
RESET, BACKOFF AND HOLD
ACKNOWLEDGE
Table 19. Reset Conditions
Floating
Floating
Driven high (Inactive)
Driven low (Read)
Driven high (Inactive)
Driven high (Inactive)
Driven low (Active)
Driven low (Receive)
Driven high (Inactive)
Driven high (Inactive)
Driven low (Inactive)
Floating
Floating
Floating
Driven low (Active)
Driven high (Inactive)
Floating (Set to input mode)
State During Reset
(HOLDA inactive)
1
Table 20 lists the condition of each processor output
pin while HOLDA is asserted (low).
A31:2
D31:0
BE3:0
W/R
ADS
WAIT
BLAST
DT/R
DEN
LOCK
BREQ
D/C
DMA
SUP
FAIL
DACK3:0
EOP3:0/TC3:0
Pins
Table 20. Hold Acknowledge
and Backoff Conditions
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Driven (High or low)
Floating
Floating
Floating
Driven high (Inactive)
Driven high (Inactive)
Driven (If output)
State During HOLDA
80960CA-33, -25, -16
35