NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet

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... To maximize utilization of hardware re- sources the DSPM contains a pipelined DSP-oriented data- path and a control logic that implements a set of DSP vec- tor commands Block Diagram Series 32000 is a registered trademark of National Semiconductor Corporation EP TM and Embedded System Processors TM are trademarks of National Semiconductor Corporation ...

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PRODUCT INTRODUCTION 1 1 NS32FX164 Special Features 2 0 ARCHITECTURAL DESCRIPTION 2 1 Register Set General Purpose Registers Address Registers Processor Status Register Configuration Register 2 ...

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Table of Contents 3 5 System Interface Power and Grounding Clocking Power Save Mode Resetting Bus Cycles Bus Status 3 5 ...

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FIGURE 2-27 TBITS Instruction Format FIGURE 2-28 SBITS Instruction Format FIGURE 2-29 SBITPS Instruction Format FIGURE 2-30 Bus Activity for a Simple BITBLT Operation FIGURE 3-1 Operating States FIGURE 3-2 Slave Processor Protocol FIGURE 3-3 Slave Processor Status Word FIGURE ...

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FIGURE 4-17 NMI Signal Timing FIGURE 4-18 Power-On Reset FIGURE 4-19 Non-Power-On Reset FIGURE 4-20 Interrupt Out TABLE 2-1 NS32FX164 Addressing Modes TABLE 2-2 NS32FX164 Instruction Set Summary TABLE 2-3 ‘op’ and ‘i’ Field Encodings TABLE 3-1 Floating-Point Instruction Protocols ...

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Product Introduction The NS32FX164 is a high speed CMOS microprocessor in the Series 32000 EP family It includes two main execution units the NS32CG16 com- patible CPU core and the DSP Module The CPU core is designed for ...

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Product Introduction (Continued) Below is a summary of the instructions that are directly ap- plicable to graphics along with their intended use Instruction Application BBAND The BITBLT group of instructions provide a BBOR method of quickly imaging characters ...

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Architectural Description Address Registers The seven address registers are used by the processor to implement specific address functions Except for the MOD register that is 16 bits wide all the others are 32 bits A ...

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Architectural Description B Reserved for use by the CPU This bit is set to 1 during the execution of the EXTBLT instruction and causes the BPU signal to become active Upon reset B is set to zero and ...

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Architectural Description The X Y and Z registers are used for addressing up to three vector operands They are 32-bit registers with three fields ADDRESS INCREMENT and WRAP-AROUND The value in the ADDRESS field specifies the address of ...

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Architectural Description EXT External Memory Reference Control Register The format of the external memory reference control regis- ter is shown in Figure 2-11 15 Reserved FIGURE 2-11 EXT Register Format The EXT register controls external references The com- ...

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... Addresses marked as Reserved in Figure 2-15 are not avail- able in the present implementation of the NS32FX164 and should not be used The top 8-Mbyte block is reserved by National Semiconductor Corporation and only a few loca- tions within this block are presently used to access the on- chip RAM array and DSP Module registers Figure 2-15 ...

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Architectural Description Following Index Bytes come any displacements (addressing constants) or immediate values associated with the select- ed addressing modes Each Disp lmm field may contain one of two displacements or one immediate value The size of a ...

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Architectural Description Addressing Modes The NS32FX164 CPU generally accesses an operand by calculating its Effective Address based on information avail- able when the operand accessed The method to be used in performing ...

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Architectural Description TABLE 2-1 NS32FX164 Addressing Modes ENCODING MODE Register 00000 Register 0 00001 Register 1 00010 Register 2 00011 Register 3 00100 Register 4 00101 Register 5 00110 Register 6 00111 Register 7 Register Relative 01000 Register ...

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Architectural Description Instruction Set Summary Table 2-2 presents a brief description of the NS32FX164 instruction set The Format column refers to the Instruction Format tables (Appendix A) The Instruction column gives the instruction as coded ...

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Architectural Description TABLE 2-2 NS32FX164 Instruction Set Summary (Continued) INTEGER COMPARISON Format Operation Operands 4 CMPi gen gen 2 CMPQi short gen 7 CMPMi gen gen disp LOGICAL AND BOOLEAN Format Operation Operands 4 ANDi gen gen 4 ...

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Architectural Description TABLE 2-2 NS32FX164 Instruction Set Summary (Continued) Format Operation Operands 5 MOVSi options MOVST options 5 CMPSi options CMPST options 5 SKPSi options SKPST options JUMPS AND LINKAGE Format Operation Operands 3 JUMP gen 0 BR ...

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Architectural Description TABLE 2-2 NS32FX164 Instruction Set Summary (Continued) FLOATING POINT Format Operation Operands 11 MOVf gen gen 9 MOVLF gen gen 9 MOVFL gen gen 9 MOVif gen gen 9 ROUNDfi gen gen 9 TRUNCfi gen gen ...

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Architectural Description 2 5 GRAPHICS SUPPORT The following sections provide a brief description of the NS32FX164 graphics support capabilities Basic discus- sions on frame buffer addressing and BITBLT operations are also provided More detailed information on the NS32FX164 ...

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Architectural Description Frame Buffer Architecture There are two basic types of frame buffer architectures plane-oriented or pixel-oriented BITBLT takes advantage of the plane-oriented frame buffer architecture’s attribute of multiple adjacent pixels-per-word facilitating the movement ...

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Architectural Description BITBLT Directions A BITBLT operation moves a rectangular block of data in a frame buffer The operation itself can be considered as a subroutine with two nested loops The loops are preceded ...

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Architectural Description curs any time the screen is moved in a purely vertical direc- tion as in scrolling text It should be noted that in both of these cases the choice of horizontal BITBLT direction may be made ...

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Architectural Description This instruction can be used within the inner loop of a block OR operation Its use assumes that the source data is ‘clean’ and does not need masking The BITWT format is shown in Figure 2-24 ...

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Architectural Description Set Bit String Syntax SBITS Setup R0 base address of the destination R1 starting bit offset (signed) R2 number of bits to set (unsigned) R3 address of string look-up table Note When the instruction terminates the ...

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Architectural Description Magnifying Compressed Data Restoring data is just one application of the SBITS and SBITPS instructions Multiplying the ‘‘length’’ operand used by the SBITS and SBITPS instructions causes the resulting pattern to ...

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Functional Description Completed Instructions When an exception is recognized after an instruction is completed the CPU has performed all of the operations for that instruction and for all other instructions executed since the last ...

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Functional Description The CPU next sends the Operation Word while applying Status Code 1101 (Transfer Slave Operand Upon receiving it the Slave Processor decodes it and at this point both the CPU and the ...

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Functional Description The Operand class columns give the Access Class for each general operand defining how the addressing modes are interpreted (see Series 32000 Instruction Set Reference Manual) The Operand Issued columns show the sizes of the oper- ...

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Functional Description FIGURE 3-4 Interrupt Dispatch and Cascade Tables Returning from an Exception Service Procedure To return control to an interrupted program one of two in- structions can be used RETT (Return from Trap) and ...

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Functional Description FIGURE 3-5 Exception Acknowledge Sequence (Continued) Direct-Exception Mode Disabled 11267– 11267 – 17 ...

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Functional Description FIGURE 3-6 Exception Acknowledge Sequence (Continued) Direct-Exception Mode Enabled 11267 – 11267 – 19 ...

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Functional Description FIGURE 3-7 Return from Trap (RETTn) Instruction Flow (Continued) Direct-Exception Mode Disabled 11267 – 20 ...

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Functional Description FIGURE 3-8 Return from Interrupt (RETI) Instruction Flow Maskable Interrupts The INT pin is a level-sensitive input A continuous low level is allowed for generating multiple interrupt requests The in- put is maskable ...

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Functional Description Vectored Mode Non-Cascaded Case In the Vectored mode the CPU uses an Interrupt Control Unit (ICU) to prioritize interrupt requests Upon re- ceipt of an interrupt request on the ...

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Functional Description FIGURE 3-10 Cascaded Interrupt Control Unit Connections (Continued 11267 – 23 ...

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Functional Description Non-Maskable Interrupt The Non-Maskable Interrupt is triggered whenever a falling edge is detected on the NMI pin The CPU performs an ‘‘Interrupt Acknowledge’’ bus cycle from Address FFFF00 when processing of this interrupt ...

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Functional Description FIGURE 3-11 Exception Processing Flowchart (Continued 11267 – 24 ...

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Functional Description Exception Acknowledge Sequences Detailed Flow For purposes of the following detailed discussion of excep- tion acknowledge sequences a single sequence called ‘‘service’’ is defined in Figure 3-12 Upon detecting any interrupt request or ...

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Functional Description TABLE 3-2 Summary of Exception Processing Exception Interrupt UND SLAVE SVC DVZ FLG BPT ILL TRC 3 3 DEBUGGING SUPPORT The NS32FX164 provides features to assist in program de- bugging Besides the Breakpoint (BPT) instruction that ...

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Functional Description The CPU core interface specifies the mapping of the DSPM internal RAM as a contiguous block within the CPU core’s address space thus making it possible for normal CPU in- structions to access and manipulate data ...

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Functional Description accumulator Bit 0 of the extended-precision argument is not used during calculations This bit is always set to ‘‘0’’ when stored back in the internal memory 15 0 (Location Less Significant Part (Location ...

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Functional Description memory areas for any purpose exactly as they would ac- cess external off-chip memory locations However when the DSPM command list execution unit is active any at- tempt to read or write a location within the ...

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Functional Description aligned real An aligned real value as described in Sec- tion extended An extended-precision real value as de- scribed in Section complex A complex value as described in ...

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Functional Description LA Load Accumulator The LA instruction loads the complex value at aligned addr into the A accumulator as a complex value Syntax LA aligned addr 00101 aligned addr Operation (complex) A (complex) mem ...

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Functional Description SXH Store X Vector Pointer Higher Half The SXH instruction stores the contents of the higher-half of the X register into the word at mem addr Syntax SXH addr 11101 addr Operation mem ...

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Functional Description Operation X ADDR X 1 Note Accumulator is not affected INCY Increment Y Vector Pointer The INCY instruction increments the Y vector pointer by one element according to the increment and the wrap Syntax EXEC INCY ...

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Functional Description Syntax EXEC DJNZ 10000 101 0110 1100 Note Accumulator is not affected DBPT Debug Breakpoint The DBPT instruction is used for implementing software de- bug breakpoint in the DSPM command-list Whenever there is ...

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Functional Description Syntax EXEC VXSTORE 10000 100 0101 0101 Operation real X Z ext address EABR for ( LENG ext mem EABR (ext address VXGATH Vector External ...

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Functional Description VARMAC Vector Aligned Real Multiply and Accumulate The VARMAC instruction performs a convolution sum of the X and Y real vectors The previous value of the accumulator is used and the result is stored in Z ...

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Functional Description Operation aligned integer X Y integer Z for ( LENG (integer low (integer high) ...

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Functional Description Operation aligned real X Y extended Z for ( LENG (extended low (extended high) ...

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Functional Description Operation real X integer Z internal register real tempX internal register integer tempA tempX X 0 tempA X 0 for ( LENG tempX) tempX X n tempA ...

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Functional Description Syntax EXEC VCPOLY 10000 101 0001 1000 Operation complex X Z real Y complex temp temp re (real temp im 0 for ( LENG n ...

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Functional Description Operation real real acc A for ( LENG (real acc) ((extended)A) A (real acc (real) A Note The term (A ...

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Functional Description For optimal noise immunity the power and ground pins should be connected to V and ground planes respective and ground planes are not used single conductors CC should be run directly from ...

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Functional Description TABLE 3-3 External Oscillator Specifications Crystal Characteristics Type Tolerance 0 005% at Stability 0 01% from Resonance 30 MHz Fundamental (Parallel) 40 MHz or 50 MHz Third Overtone (Parallel) Maximum Series Resistance Maximum ...

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Functional Description In general a SETCFG instruction must be executed in the reset routine in order to properly configure the CPU The options should be combined and executed in a single in- struction For example to declare vectored ...

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Functional Description (Continued) FIGURE 3-20 Bus Connections 11267 – 32 ...

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Functional Description (Continued) FIGURE 3-21 Read Cycle Timing 11267 – 33 ...

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Functional Description (Continued) FIGURE 3-22 Write Cycle Timing 11267 – 34 ...

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Functional Description At this time the signals TSO (Timing State Output) DBE (Data Buffer Enable) and either RD (Read Strobe (Write Strobe) will also be activated The T3 state provides for access time requirements and it ...

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Functional Description FIGURE 3-23 Cycle Extension of a Read Cycle Instruction Fetch Cycles Instructions for the NS32FX164 CPU are ‘‘prefetched’’ that is they are input before being needed into the next available entry of ...

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Functional Description Interrupt Control Cycles Activating the INT or NMI pin on the CPU will initiate one or more bus cycles whose purpose in interrupt control rather than the tranfer of instructions or data ...

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Functional Description Special Bus Cycles Special bus cycles are performed during CPU accesses to the DSP Module (DSPM) registers or internal RAM These cycles may be used by external logic to track CPU activities ...

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Functional Description Note CPU samples Data Bus here FIGURE 3-25 Slave Processor Read Cycle The CPU does not pulse the Address Strobe (ADS) and no bus signals are generated The direction of a transfer is de- termined by ...

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Functional Description Note Slave Processor samples Data Bus here FIGURE 3-26 Slave Processor Write Cycle Data Access Sequences The 24-bit address provided by the NS32FX164 is a byte address that is it uniquely identifies ...

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Functional Description Cycle Type Address HBE 1 Odd Byte A 2 Even Byte Even Double-Word Access Sequence Byte 3 1 Even Word A 1 Even Word Odd Double-Word Access Sequence ...

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Functional Description How quickly the CPU releases the bus depends on whether it is idle on the bus at the time the HOLD request is made as the CPU must always complete the current bus cycle Figure 3-29 ...

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Functional Description FIGURE 3-30 HOLD Timing (Bus Initially Not Idle) (Continued 11267 – 42 ...

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Functional Description Instruction Status In addition to the four bits of Bus Cycle status (ST0– 3) the NS32FX164 CPU also presents Instruction Status informa- tion on three separate pins These pins differ from ST0 ...

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Device Specifications (Continued) BPU BPU Cycle This signal is activated during a bus cycle to en- able an external BITBLT processing unit The EXTBLT instruction activates this signal Note BPU is low (Active) only during bus cycles involving ...

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Device Specifications (Continued) Order Number NS32FX164V-20 NS32FX164V-25 NS32FV16-20 NS32FV16-25 NS32FX161V-15 or NS32FX161-20 Note Pins 65 and 66 must be connected to GND or V 68-Pin PCC Package Bottom View NS Package Number V68A FIGURE 4-1 Connection Diagram CC ...

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... Device Specifications 4 2 ABSOLUTE MAXIMUM RATINGS If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature under Bias Storage Temperature ELECTRICAL CHARACTERISTICS T Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage ...

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Device Specifications Timing Tables Output Signals Internal Propagation Delays NS32FX161-15 NS32FX164-20 NS32FX164-25 The output to input timings (e g address to data-in) are at least 2 ns better than the worst ...

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Device Specifications Timing Tables (Continued Output Signals Internal Propagation Delays NS32FX161-15 NS32FX164-20 NS32FX164-25 Symbol Figure Description t 4-4 DDIN Signal Valid DDINv t 4-4 DDIN Signal Hold DDINh t 4-7 DDIN ...

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Device Specifications Timing Tables (Continued Output Signals Internal Propagation Delays NS32FX161-15 NS32FX164-20 NS32FX164-25 Symbol Figure Description t 4-6 IAS Signal Active After R E CTTL T1 IASa t 4-6 IAS Signal ...

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Device Specifications Input Signal Requirements NS32FX161-15 NS32FX164-20 and NS32FX164-25 (Continued) Symbol Figure Description t 4-18 Power Stable to After V PWR RSTI R E (Note 2) t 4-19 RSTI Pulse Width ...

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Device Specifications (Continued Timing Diagrams FIGURE 4-4 Read Cycle 11267 – 46 ...

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Device Specifications (Continued) FIGURE 4-5 Write Cycle 11267 – 47 ...

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Device Specifications (Continued) FIGURE 4-6 Special Bus Cycle 11267 – 48 ...

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Device Specifications (Continued) Note When the bus is not idle HOLD must be asserted before the rising edge of CTTL of the timing state that precedes state T4 in order for the request to be acknowledged FIGURE 4-7 ...

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Device Specifications (Continued) FIGURE 4-8 HOLD Timing (Bus Initially Idle 11267– 50 ...

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Device Specifications (Continued) Note 1 ADS must be deactivated before state T4 of the external DMA controller cycle Note 2 During an external DMA cycle WAIT1–2 must be kept inactive unless they are monitored by the DMA Controller ...

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Device Specifications (Continued) FIGURE 4-10 Slave Processor Write Timing After transferring the last operand to the FPU the CPU turns OFF the output driver and holds SPC high with an internal 11267– 52 FIGURE ...

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Device Specifications (Continued) Note ILO may be asserted more than one clock cycle before the beginning of an interlocked access TL EE 11267 – 55 FIGURE 4-13 PFS Signal Timing FIGURE 4-14 ILO Signal Timing FIGURE 4-15 Clock ...

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Device Specifications (Continued) Note 1 Once INT is asserted it must remain asserted until it is acknowledged Note 2 INTA is the Interrupt Acknowledge bus cycle (not a CPU signal) Refer to Section FIGURE 4-16 ...

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Device Specifications (Continued) Note 1 During Reset the HOLD signal must be kept high Note 2 After RSTI is deasserted the first bus cycle will be an instruction fetch at address zero FIGURE 4-19 Non-Power-On Reset FIGURE 4-20 ...

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Appendix A Instruction Formats NOTATIONS i Integer Type Field (Byte (Word (Double Word Floating-Point Type Field (Std Floating 32 bits (Long Floating 64 ...

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Appendix A Instruction Formats Format 5 MOVS 0000 BITWT b CMPS 0001 TBITS b SETCFG 0010 BBAND b SKPS 0011 SBITPS b BBSTOD 0100 BBFOR b EXTBLT 0101 SBITS b BBOR 0110 BBXOR b MOVMP 0111 b No Operation on ...

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Appendix A Instruction Formats Format 14 Trap (UND) Always Format 15 Trap (UND) Always Format 16 Trap (UND) Always Format 17 Trap (UND) Always Note 1 Opcode not defined CPU treats like MOVf First operand has access class of read ...

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Appendix B Instruction Execution Times This section provides the necessary information to calculate the instruction execution times for the NS32FX164 The following assumptions are made The entire instruction with all displacements and imme- Y diate operands is assumed to be ...

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Appendix B Instruction Execution Times TOPi If operand register or is immediate then TOPi 0 e else if i byte then TOPi TOPB e e else if i word then TOPi TOPW e e else (i double-word) ...

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Appendix B Instruction Execution Times TEX Calculation Operand register operand memory This means that we have to use the table values for the case The following parameter values are obtained from Table B-2 ...

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Appendix B Instruction Execution Times TABLE B-1 Basic Instructions (Continued) Mnemonic TEA1 TEA2 TOPB BICPSRB 1 1 BICPSRW 1 BISPSRB 1 1 BISPSRW 1 BPT BR BSR CASEi 1 CBITi CBITIi CHECKi ...

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Appendix B Instruction Execution Times TABLE B-1 Basic Instructions (Continued) Mnemonic TEA1 TEA2 TOPB INDEXi 1 1 INSi INSSi 1 1 JSR 1 JUMP 1 LPRi 1 LSHi MEIi 1 1 MODi 1 1 ...

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Appendix B Instruction Execution Times TABLE B-1 Basic Instructions (Continued) Mnemonic TEA1 TEA2 TOPB REMi 1 1 RESTORE RET RETI 1 2 RETT ROTi RXP Scondi 1 1 SAVE SBITi SBITIi 1 1 ...

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Appendix B Instruction Execution Times TABLE B-2 Floating-Point Instructions CPU Portion Mnemonic TEA1 TEA2 TOPD ADDf SUBf 1 f MULf DIVf MOVf ABSf 1 f NEGf MOVFL 1 1 ...

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Appendix B Instruction Execution Times B 2 SPECIAL GRAPHICS INSTRUCTIONS This section provides the execution times for the special graphics instructions Table B-3 lists the average instruction execution times for different shift values and for a no-wait- state system design ...

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Appendix B Instruction Execution Times TABLE B-3 Average Instruction Execution Times with No Wait-States (Continued) Instruction Number of Clock Cycles BITWT shift 28 a EXTBLT (11 a ...

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Appendix B Instruction Execution Times Adjust Register Instructions Instruction Cycles INCX INCY INCZ DECX DECY DECZ Flow Control Instructions Instruction Cycles NOPR HALT DJNZ DBPT Internal Memory Move Instructions Instruction Cycles VRMOV 2 leng c leng VARMOV 2 c VRGATH ...

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