GDPXA255A0E400 Intel, GDPXA255A0E400 Datasheet - Page 24

• Manufacturer Part Number: GDPXA255A0E400
• Description: IC MICRO PROCESSOR 400MHZ 256BGA
• Manufacturer: Intel

Specifications of GDPXA255A0E400

• Processor Type: XScale®
• Speed: 400MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 852106

Documentation Changes
D1.
Affected Docs:
Issue:
D2.
Affected Docs:
Issue:
D3.
Affected Docs:
Issue:
0
0
The physical address of the Divisor Latch Register High (DLH) Bit Definitions
incorrect.
Intel® PXA255 Processor Developer’s Manual
Table 17-5 states:
It should state:
ROR bit should reset when SSE Bit is cleared
Intel® PXA255 Processor Developer’s Manual
In 8.7.1 paragraph 10, the description of the Synchronous Serial Port Enable (SSE) currently states:
The SSP’s control registers and the SSSR[ROR] bits are not reset when SSCR0[SSE] is cleared.
It should state:
The SSP’s control registers are not reset when SSCR0[SSE] is cleared.
'End/Error in FIFO' interrupt occurs at or below trigger level
Intel® PXA255 Processor Developer’s Manual
Table 11-6 states:
It should state:
Physical Address 0x4160_0000
Physical Address 0x4160_0004
EIF
EIF
End/error in FIFO (read-only).
0 – Bits 8–10 are not set within any of the entries below the trigger level of the receive
FIFO. Receive FIFO DMA service requests are enabled.
1 – One or more tag bits (8 – 10) are set within the entries below the trigger level of the
receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
This interrupt is not maskable in the FICP. Once the bad bytes have been removed from
the FIFO and EIF is cleared, DMA requests are automatically enabled.
End/error in FIFO (read-only).
0 – Bits 8–10 are not set within any of the entries at or below the trigger level of the receive
FIFO. Receive FIFO DMA service requests are enabled.
1 – One or more tag bits (8 – 10) are set within the entries at or below the trigger level of
the receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
This interrupt is not maskable in the FICP. Once the bad bytes have been removed from
the FIFO and EIF is cleared, DMA requests are automatically enabled.
is