QU80386EXTC25 Intel, QU80386EXTC25 Datasheet - Page 19

• Manufacturer Part Number: QU80386EXTC25
• Description: IC INT PROC 5V 25MHZ 132QFP
• Manufacturer: Intel

Specifications of QU80386EXTC25

• Processor Type: 386EX
• Features: 32-bit, Extended Temp
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863826

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Datasheet
Functional Description
The Intel386 EX microprocessor is a fully static, 32-bit processor optimized for embedded
applications. It features low power and low voltage capabilities, integration of many commonly
used DOS-type peripherals, and a 32-bit programming architecture compatible with the large
software base of Intel386 processors. The following sections provide an overview of the integrated
peripherals.
Clock Generation and Power Management Unit
The clock generation circuit includes a divide-by-two counter, a programmable divider for
generating a prescaled clock (PSCLK), a divide-by-two counter for generating baud-rate clock
inputs, and Reset circuitry. The CLK2 input provides the fundamental timing for the chip. It is
divided by two internally to generate a 50% duty cycle Phase1 (PH1) and Phase 2 (PH2) for the
core and integrated peripherals. For power management, separate clocks are routed to the core
(PH1C/PH2C) and the peripheral modules (PH1P/PH2P). To help synchronize with external
devices, the PH1P clock is provided on the CLKOUT output pin.
Two Power Management modes are provided for flexible power-saving options. During Idle mode,
the clocks to the CPU core are frozen in a known state (PH1C low and PH2C high), while the
clocks to the peripherals continue to toggle. In Powerdown mode, the clocks to both core and
peripherals are frozen in a known state (PH1C low and PH2C high). The Bus Interface Unit will
not honor any DMA, DRAM refresh, or HOLD requests in Powerdown mode because the clocks to
the entire device are frozen.
Chip-select Unit
The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the
appropriate chip-selects. The individual chip-selects become valid in the same bus state as the
address and become inactive when either a new address is selected or the current bus cycle is
complete.
The CSU is divided into eight separate chip-select regions, each of which can enable one of the
eight chip-select pins. Each chip-select region can be mapped into memory or I/O space. A
memory-mapped chip-select region can start on any 2
depending upon the mask register). An I/O-mapped chip-select region can start on any 2
address location (where n = 0–15, depending upon the mask register). The size of the region is also
dependent upon the mask used.
Interrupt Control Unit
The Intel386 EX processor’s Interrupt Control Unit (ICU) contains two 8259A modules connected
in a cascade mode. These modules are similar to the industry-standard 8259A architecture.
The Interrupt Control Unit directly supports up to ten external (INT9:0) and up to eight internal
interrupt request signals. Pending interrupt requests are posted in the Interrupt Request Registers,
which contain one bit for each interrupt request signal. When an interrupt request is asserted, the
corresponding Interrupt Request Register bit is set. The 8259A modules can be programmed to
Intel386™ EX Embedded Microprocessor
(n+1)
Kbyte address location (where n = 0–15,
(n+1)
byte
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